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Reseach Article

Performance Comparison of Mesh and Folded Torus Network under Broadcasting, using Distance Vector Routing Algorithm

by Narander Kumar, Shalini Agarwal, Pradeep Keshwani
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 65 - Number 11
Year of Publication: 2013
Authors: Narander Kumar, Shalini Agarwal, Pradeep Keshwani
10.5120/10972-6112

Narander Kumar, Shalini Agarwal, Pradeep Keshwani . Performance Comparison of Mesh and Folded Torus Network under Broadcasting, using Distance Vector Routing Algorithm. International Journal of Computer Applications. 65, 11 ( March 2013), 39-43. DOI=10.5120/10972-6112

@article{ 10.5120/10972-6112,
author = { Narander Kumar, Shalini Agarwal, Pradeep Keshwani },
title = { Performance Comparison of Mesh and Folded Torus Network under Broadcasting, using Distance Vector Routing Algorithm },
journal = { International Journal of Computer Applications },
issue_date = { March 2013 },
volume = { 65 },
number = { 11 },
month = { March },
year = { 2013 },
issn = { 0975-8887 },
pages = { 39-43 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume65/number11/10972-6112/ },
doi = { 10.5120/10972-6112 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:18:38.398150+05:30
%A Narander Kumar
%A Shalini Agarwal
%A Pradeep Keshwani
%T Performance Comparison of Mesh and Folded Torus Network under Broadcasting, using Distance Vector Routing Algorithm
%J International Journal of Computer Applications
%@ 0975-8887
%V 65
%N 11
%P 39-43
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In the modern technology of communication architecture, network on chip is widely used as communication architecture. Network on chip topologies are becoming a backbone of communication architectures. Network on chip provides a good integration of huge amount of storage on chip blocks as well as computational also. Network on chip handled the unfavorable conditions and it provides the scalability to the architecture. Mesh and folded torus architectures are most commonly used architecture for network on chip communication. Here, we compare the performance of Mesh and Folded torus network architecture on chip, on the basis of different parameters under broadcasting with the help of distance vector routing algorithm. To evaluate the performance of Mesh and folded torus network on chip in the simulation environment, we use the network simulator (NS-2) in the Linux platform.

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Index Terms

Computer Science
Information Sciences

Keywords

Network on chip Performance Mesh Folded Torus Latency