The week's pick
Reseach Article
Performance Comparison of Mesh and Folded Torus Network under Broadcasting, using Distance Vector Routing Algorithm
by
Narander Kumar,
Shalini Agarwal,
Pradeep Keshwani
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 65 - Number 11 |
| Year of Publication: 2013 |
| Authors: Narander Kumar, Shalini Agarwal, Pradeep Keshwani |
10.5120/10972-6112
|
Narander Kumar, Shalini Agarwal, Pradeep Keshwani . Performance Comparison of Mesh and Folded Torus Network under Broadcasting, using Distance Vector Routing Algorithm. International Journal of Computer Applications. 65, 11 ( March 2013), 39-43. DOI=10.5120/10972-6112
@article{
10.5120/10972-6112,
author = {
Narander Kumar,
Shalini Agarwal,
Pradeep Keshwani
},
title = { Performance Comparison of Mesh and Folded Torus Network under Broadcasting, using Distance Vector Routing Algorithm },
journal = {
International Journal of Computer Applications
},
issue_date = { March 2013 },
volume = { 65 },
number = { 11 },
month = { March },
year = { 2013 },
issn = { 0975-8887 },
pages = {
39-43
},
numpages = {9},
url = {
https://ijcaonline.org/archives/volume65/number11/10972-6112/
},
doi = { 10.5120/10972-6112 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:18:38.398150+05:30
%A Narander Kumar
%A Shalini Agarwal
%A Pradeep Keshwani
%T Performance Comparison of Mesh and Folded Torus Network under Broadcasting, using Distance Vector Routing Algorithm
%J International Journal of Computer Applications
%@ 0975-8887
%V 65
%N 11
%P 39-43
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract
In the modern technology of communication architecture, network on chip is widely used as communication architecture. Network on chip topologies are becoming a backbone of communication architectures. Network on chip provides a good integration of huge amount of storage on chip blocks as well as computational also. Network on chip handled the unfavorable conditions and it provides the scalability to the architecture. Mesh and folded torus architectures are most commonly used architecture for network on chip communication. Here, we compare the performance of Mesh and Folded torus network architecture on chip, on the basis of different parameters under broadcasting with the help of distance vector routing algorithm. To evaluate the performance of Mesh and folded torus network on chip in the simulation environment, we use the network simulator (NS-2) in the Linux platform.
References
- L. Benini and G. De Micheli, "Networks on chip: a new paradigm for systems on chip design," Proceedings, Design, Automation and Test in Europe Conference and Exhibition, pp. 418–419, 2002.
- L. Benini and G. De Micheli, "Powering networks on chips," Proceedings, the 14th International Symposium on System Synthesis, pp. 33–38, 2001.
- Lee, H. G. , Chang, N. , Ogras, U. Y. , and Marculescu, R. , "On-Chip Communication Architecture Exploration: A quantitative evaluation of point to point, bus and network on chip approaches. " ACM trans. Des. Autom. Electron. Sys. , 12, 3, 1-20, 2007.
- L. Benini and G. D. Micheli, "Networks on chips: a new Soc paradigm," IEEE transaction on Computer, vol. 35, no. 1, pp. 70–78, Jan. 2002.
- P. Guerrier and A. Greiner, "A generic architecture for on-chip packet switched interconnections," Proceeding of DATE. ACM Press, 2000, pp. 250–256.
- W. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks," Proceedings of the Design Automation Conference, 2001.
- G. D. Micheli and L. Benini, "Network architecture: Principles and examples," in Networks-on Chips: Technology and Tools, ser. The Morgan Kaufmann Series in Systems on Silicon, G. D. Micheli and L. Benini, Eds. Morgan Kaufmann, ch. 5, pp. 1–22, Jul. 2006.
- S. Vangal et al. "An 80-Tile 1. 28TFLOPS Network-on-Chip in 65nm CMOS. " Proceedings of the International Solid-State Circuits Conference, Feb. 2007.
- W. J. Dally and B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks," Proceedings of the Design Automation Conference, pages 684–689, June 2001.
- J. Duato, S. Yalamanchili, and L. Ni, "Interconnection Networks—An Engineering Approach," Morgan Kaufmann, 2002.
- S. B. Akers and B. Krishnamurthy, "A Group-Theoretic Model for Symmetric Interconnection Networks," IEEE Transactions on Computers, vol. C-38, no. 4, pp. 555–566, April 1989.
- F. Karim, A. Nguyen, and S. Dey, "An Interconnect Architecture for Networking Systems on Chip," IEEE Micro, vol. 22, no. 5, pp 36–45, September/October 2002.
- Adriahantenaina, H. Charlery, A. Greiner, L. Mortiez, and C. A. Zeferino, "Spin: A scalable, Packet Switched, on Chip Micro-Network," In DATE 03 Embedded Software Forum, pages 70–73, 2003.
- W. J. Dally and C. L. Seitz, "The Torus Routing Chip," Technical Report 5208: TR: 86, Computer Science Dept. , California Inst. of Technology, pp. 1-19, 1986.
- Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh, "Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures," IEEE Trans. Computers, vol. 54, no. 8, pp 1025-1040, 2005.
- Yu-hang Liu, Ming-fa Zhu, Li-min Xaio, Jue Wang, "Asymmetrical topology and entropy-based heterogeneous link for many-core massive data communication", Springer Journal of Cluster Computing, January 2013, DOI 10. 1007/s10586-012-0238-3.
- Yaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang, Weichen Liu and Mahdi Nikdast, "A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip", ACM Journal on Emerging Technologies in Computing Systems, Volume 8, No. 1, Article 5, February 2012.
- Sameer Bataineh, Ajmad Odet-Allah, Raed Al-Omari, "Reliability of mesh and torus topologies in the presence of faults", Springer Journal of Telecommunication Systems, Volume 10, Issue 3-4, pp 389-408, December 1998, Issn 1572-9451, DOI 1023/A:1019187605001.
- Pedram Rajabzadeh, Hamid Sarbazi-Azad, Hamid-Reza Zarandi, Ebrahim Khodaie, Hashem Hashemi-Najafabadi, Mohamed Ould-Khaoua, "Performance modelling of n-dimensional mesh networks", Elsevier Journal of Performance Evaluation, Volume 67, Issue 12, pp 1304-1323, December 2010, ISSN 0166-5316.
- Kai Feng, Yaoyao Ye, Jiang Xu, "A formal study on topology and floor plan characteristics of mesh and torus-based optical networks-on-chip" Elsevier Journal of Microprocessors and Microsystems, 2012. doi:10. 1016/j. micpro. 2012. 06. 010.
- Ajima, Y, Sumimoto, S. , Shimizu, T. , "Tofu: A 6-D Mesh/Torus Interconnect for Exascale Computers", IEEE Journal of Computer, Volume 42, No. 11, pp 36-40, November 2009, DOI: 10. 1109/MC. 2009. 370.
- J. F. Fang, J. Y. Hsiao, C. Y. Tang, "Embedding meshes and TORUS networks on to degree-four chordal rings", IEEE Proceedings – Computers and Digital Techniques, Volume 145, Issue 2, pp 73-80, March 1998.
- Mohammad Reza Nouri rad, Reza Kourdy, "Performance Comparison of 3D-Mesh and 3D-Torus Network-on-Chip", Journal of Computer, Volume 4, Issue 1, pp 71-82, January 2012, ISSN 2151-9617.
- M. M. Hafizur Rahman, Yukinori Sato, and Yasushi Inoguchi, "High Performance Hierarchical Torus Network Under Adverse Traffic Patterns" Journal of Network © Academy Publisher, VOL. 7, NO. 3, pp 456-467, March 2012.
- Xingang Ju, Liang Yang, "NoC Research and Practice: Design and Implementation of 2×4 2D-Torus Topology" International Journal of Information Technology and Computer Science © MECS press, pp 50-56, 2011.
- Lalit Kishore Arora, Rajkumar, "Performance Evaluation of Mesh with Source Routing for Packet Loss", International Journal of Scientific Research Engineering & Technology (IJSRET) Volume 1, Issue 5, pp 124-129, August 2012.
- Yi-Ran Sun, Shashi Kumar, Axel Jantsch, "Simulation and Evaluation for a Network on ChipArchitecture Using NS-2", the Department of Microelectronics & Information Technology (IMIT),
Index Terms
Computer Science
Information Sciences
Keywords