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FPGA-based New Hybrid Adder Design with the Optimal Bit-Width Configuration
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 65 - Number 11 |
| Year of Publication: 2013 |
| Authors: Mahmoud A. M. Alshewimy, Ahmet Sertbas |
10.5120/10968-6100
|
Mahmoud A. M. Alshewimy, Ahmet Sertbas . FPGA-based New Hybrid Adder Design with the Optimal Bit-Width Configuration. International Journal of Computer Applications. 65, 11 ( March 2013), 15-19. DOI=10.5120/10968-6100
Abstract
This paper presents FPGA-based design of hybrid adder with the optimal bit-width configuration(out of alarge number of possible configurations) of each of the sub-adders constitute the proposed hybrid adder using a high level automated methodology. Algebraicoptimization model for the hybrid adderis built to produce the best choice of types and bit-widths of the sub-adders. In context of this work, several classes of parallel adders are designed and its performance is evaluated to serve as sub-adders inside the hybrid adder. The results show that the proposed model gains a high flexibility in allowing design tradeoffs between the performance criteria delay and areaand successfully to generate the optimalbit-width configurations of the hybrid adder.
References
- Lynch, T. and Swartzlander, E. E. ,"A spanning Tree Carry Lookahead Adder", IEEE Trans. on Computers, 41 (August 1992), 931-939,1993.
- Wang, Y. , Pai, C. , and Song, X. , "The Design of Hybrid Carry-Lookahead/Carry–Select Adders", IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 49, no. 1, 2002.
- Li, J. , Yu, J. and Huang, Y. , "A Design Methodology for Hybrid Carry-Lookahead/Carry-Select Adders with Reconfigurability", in Proc. 15th VLSI/CAD Symp. , (Pintung), 2005.
- Lakshmanan, Meaamar,A. , and Othman,M. ,"High-Speed Hybrid Parallel-Prefix Carry-SelectAdder Using Ling's Algorithm", ICSE2006 Proc. , Kuala Lumpur, Malaysia, 2006.
- Zimmermann, R. 1997. Binary Adder Architectures for Cell – Based VLSI and their Synthesis, Thesis (Phd), Swiss Federal Institute of Technology, Zurich.
- PARHAMI, B. 2000. Computer Arithmetic: Algorithms and Hardware Designs, Oxford University Press, USA.
- Sklansky,J. , "Conditional sum addition logic", IRE Trans. Electron. Comput. , vol. EC-9, no. 6, pp. 226–231, June 1960.
- Brent,R. P. and Kung,H. T. , "A regular layout for parallel adders", IEEE Trans. Comput. , vol. 31, no. 3, pp. 260–264, Mar. 1982.
- Vanderbei, R. J. 2001. Linear Programming: Foundations and Extensions. 2nd Ed. , USA.
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