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FPGA-based New Hybrid Adder Design with the Optimal Bit-Width Configuration
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 65 - Number 11 |
| Year of Publication: 2013 |
| Authors: Mahmoud A. M. Alshewimy, Ahmet Sertbas |
10.5120/10968-6100
|
Mahmoud A. M. Alshewimy, Ahmet Sertbas . FPGA-based New Hybrid Adder Design with the Optimal Bit-Width Configuration. International Journal of Computer Applications. 65, 11 ( March 2013), 15-19. DOI=10.5120/10968-6100
Abstract
This paper presents FPGA-based design of hybrid adder with the optimal bit-width configuration(out of alarge number of possible configurations) of each of the sub-adders constitute the proposed hybrid adder using a high level automated methodology. Algebraicoptimization model for the hybrid adderis built to produce the best choice of types and bit-widths of the sub-adders. In context of this work, several classes of parallel adders are designed and its performance is evaluated to serve as sub-adders inside the hybrid adder. The results show that the proposed model gains a high flexibility in allowing design tradeoffs between the performance criteria delay and areaand successfully to generate the optimalbit-width configurations of the hybrid adder.
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