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Design of New Low Leakage Power Domino XOR Circuit
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 65 - Number 1 |
| Year of Publication: 2013 |
| Authors: Amit Kumar Pandey, Jayant Kumar Tiwari, Ram Awadh Mishra, Rajendra Kumar Nagaria, Manish Tiwari |
10.5120/10890-5787
|
Amit Kumar Pandey, Jayant Kumar Tiwari, Ram Awadh Mishra, Rajendra Kumar Nagaria, Manish Tiwari . Design of New Low Leakage Power Domino XOR Circuit. International Journal of Computer Applications. 65, 1 ( March 2013), 28-32. DOI=10.5120/10890-5787
Abstract
In this paper, a new XOR gate is proposed. Proposed circuit adopts mixed N-type and P-type transistors in the pull down network and current mirror at the footer transistor. This topology reduces leakage power consumption. Simulation parameters are measured at 25°C and 110°C. Proposed circuit reduces leakage power consumption up to 51. 7% at 25°C and 56% at 110°C as compared to standard N-type domino XOR gate. Similarly, proposed circuit reduces leakage power consumption up to 47. 28% at 25°C and 51. 1% at 110°C as compared to standard P-type domino XOR gate.
References
- Nowka. K. J and Galambos. T, 1998, "Circuit design techniques for a gigahertz integer microprocessor",IEEE International Conference on Computer Design,pp. 11-16.
- Agarwal. A. K. , Wairya. S, Nagaria. R. K and Tiwari. S, 2009, "Mixed gate diffusion input full adder topology for high speed low power digital circuits",World Applied Sciences Journal (WASJ:Special Issue of Computer & IT), IDOSI Publication,vol. 7,pp. 138-144.
- Mishra. S. S, Wairya. S, Nagaria. R. K and Tiwari. S, July 2009, "New deisgn methodologies for high speed low power XOR-XNOR circuits", Journal of World Academy of Science, Engineering and Technology (WASET), vol. 55, no. 35,pp. 200-206.
- Chowdhary. S. R, Banerjee. A, Roy. A and Saha. H, 2008, "A high speed 8 transistor full adder design using novel 3 transistor XOR gates", International Journal of Electrical and Computer Engineering,vol. 3,no. 12,pp. 784-790.
- Wairya. S, Nagaria. R. K and Tiwari. S, 2012, "Comparative performance analysis of XOR-XNOR function based high speed CMOS full adder circuits for low voltage VLSI design", International Journal of VLSI design and Communication Systems (VLSICS), AIRCC Publication, vol. 3, no. 2,pp. 221-242.
- Amirabadi. A, Kusha. A. A, Mortazavi. Y and Nourani. M, 2007, "Clocked delayed domino logic with efficient variable threshold voltage keeper", IEEE Transactions on Very Large Scale Integration (VLSI) Systems,vol. 15,no. 2,pp. 125-134.
- Kursun. V and Friedman. E. G, 2003, "Domino logic with variable threshold voltage keeper",IEEE Transactions on Very Large Scale Integration(VLSI) Systems,vol. 11,no. 6,pp. 1080-1093.
- Abdollahi. A, Fallah. F and Pedram. M, 2004, "Leakage current reduction in CMOS VLSI circuits by input vector control", IEEE Transactions on Very Large Scale Integration (VLSI) System, vol. 12, no. 6, pp. 140-153.
- Kao. J. T and Chandrakasan. A. P, 2000, "Dual threshold voltage techniques for low power digital circuits", IEEE Transaction on Solid-State Circuits,vol. 35,no. 7,pp. 1009-1018.
- Keshavarzi. A, Narendra. S, Borkar. S,Hawkins. C. F and Roy. K. V, 1999, " Technology scaling behaviours of optimum reverse body bias for standby leakage power reduction in CMOS IC's", Int. Sympos. Low Power Electron Design,pp. 252-254.
- Liu. Z and Kursun. V, 2006, " Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current", Microelectronics Journal,vol. 37,pp. 812-820.
- Liu. Z and Kursun. V, 2007, "PMOS-only sleep switch dual-threshold voltage domino logic in sub-65nm CMOS technologies",IEEE Transactions on Very Large Scale Integration (VLSI)Systems,vol. 15,no. 12,pp. 1311-1319.
- Wang. J,Gong. N,Hou. L, Peng. X, Sridhar. R, and Wu. W, 2011, "Leakage current, active power, and delay analysis of dynamic dual Vt CMOS circuits under P-V-T fluctuations", Microelectronics Reliability, vol. 51, pp. 1498-1502.
- Gong. N, and Guo. B, 2008, "Analysis and optimaization of leakage current characteristics in sub-65nm dual Vt footed domino circuits", Microelectronics Journal,vol. 39,pp. 1149-1155.
- Liu. Z and Kursun. V, 2006, "Leakage power characteristics of dynamic circuits in nanometer CMOS technologies", IEEE Transaction on Circuits and Systems,vol. 53,no. 8,pp. 692-696.
- Wang. J, Gong. N, Hou. L, Peng. X, Geng. S and Wu. W, 2011, "Low power and high performance dynamic CMOS XOR/XNOR gate design", Microelectronics Engineering,vol. 88,pp. 2781-2784.
- Pandey. A. K ,Mishra. V,Mishra. R. A,Nagaria. R. K and Rao. V. K, December 2012,"Conditional precharge dynamic bufer circuit", International Journal of Computer Applications,vol. 60,no. 6,pp. 45-52.
- Berkeley Predictive Technology Model (BPTM), http://www. device. eecs. berkeley. edu/wptm/ download.
- Pandey. A. K,Mishra. R. A and Nagaria. R. K, 2013, "Leakage power analysis of domino XOR gate", ISRN Electronics,Hindawi,Article Id 271316,vol. 2013,pp. 1-7.
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