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Design of New Low Leakage Power Domino XOR Circuit

by Amit Kumar Pandey, Jayant Kumar Tiwari, Ram Awadh Mishra, Rajendra Kumar Nagaria, Manish Tiwari
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 65 - Number 1
Year of Publication: 2013
Authors: Amit Kumar Pandey, Jayant Kumar Tiwari, Ram Awadh Mishra, Rajendra Kumar Nagaria, Manish Tiwari
10.5120/10890-5787

Amit Kumar Pandey, Jayant Kumar Tiwari, Ram Awadh Mishra, Rajendra Kumar Nagaria, Manish Tiwari . Design of New Low Leakage Power Domino XOR Circuit. International Journal of Computer Applications. 65, 1 ( March 2013), 28-32. DOI=10.5120/10890-5787

@article{ 10.5120/10890-5787,
author = { Amit Kumar Pandey, Jayant Kumar Tiwari, Ram Awadh Mishra, Rajendra Kumar Nagaria, Manish Tiwari },
title = { Design of New Low Leakage Power Domino XOR Circuit },
journal = { International Journal of Computer Applications },
issue_date = { March 2013 },
volume = { 65 },
number = { 1 },
month = { March },
year = { 2013 },
issn = { 0975-8887 },
pages = { 28-32 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume65/number1/10890-5787/ },
doi = { 10.5120/10890-5787 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:21:05.050840+05:30
%A Amit Kumar Pandey
%A Jayant Kumar Tiwari
%A Ram Awadh Mishra
%A Rajendra Kumar Nagaria
%A Manish Tiwari
%T Design of New Low Leakage Power Domino XOR Circuit
%J International Journal of Computer Applications
%@ 0975-8887
%V 65
%N 1
%P 28-32
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper, a new XOR gate is proposed. Proposed circuit adopts mixed N-type and P-type transistors in the pull down network and current mirror at the footer transistor. This topology reduces leakage power consumption. Simulation parameters are measured at 25°C and 110°C. Proposed circuit reduces leakage power consumption up to 51. 7% at 25°C and 56% at 110°C as compared to standard N-type domino XOR gate. Similarly, proposed circuit reduces leakage power consumption up to 47. 28% at 25°C and 51. 1% at 110°C as compared to standard P-type domino XOR gate.

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Index Terms

Computer Science
Information Sciences

Keywords

Domino Delay Gate oxide leakage current Leakage power consumption A. C noise margin

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