The attributes of transistors such as length, width or oxide thickness are being scaled down when integrated circuits are fabricated. This process variation becomes important at smaller process nodes as the variation becomes a larger percentage of the full length or width of the device. This transistor sizing causes measurable and predictable variance in the output performance of all circuits. In this work, PIFA antenna with LNA co-design has been implemented using two different technologies. First technology used, is the industry standard 180-nm CMOS-based technology family which includes both high-speed analog radio frequency (RF) CMOS and leading-edge silicon germanium (SiGe) BiCMOS technologies. Second technology used is 45-nm CMOS-based technology which implements transistors with dimensions of 120nm. The PIFA is designed to be used in low GHz Smart Dust Wireless Sensor Network, where no conventional Electrically Small Antennas (ESA) can be applied directly. The reflection co- efficients, noise figure and noise sensitivity have been calculated for the design using both the technologies. The variation in the performance of the circuit and the benefits of transistor sizing has been discussed with simulated results.

SDWSN LNA PIFA ESA