The week's pick
Reseach Article
Simulation of Vedic Multiplier in DCT Applications
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 63 - Number 16 |
| Year of Publication: 2013 |
| Authors: Vaijyanath Kunchigi, Linganagouda Kulkarni, Subhash Kulkarni |
10.5120/10552-5744
|
Vaijyanath Kunchigi, Linganagouda Kulkarni, Subhash Kulkarni . Simulation of Vedic Multiplier in DCT Applications. International Journal of Computer Applications. 63, 16 ( February 2013), 27-32. DOI=10.5120/10552-5744
Abstract
This paper illustrates the simulation of Vedic multiplier in 2-D DCT. The input data is first divided into NxN blocks, each block s of 8x8 size and 2-D DCT is applied on each of these 8x8 block and 2-D DCT is applied to reconstruct the image. The proposed 2-D DCT design uses Urdhva Tiryagbhyam a Vedic multiplication sutra and the Simulations with MATLAB prove that the proposed design is compared to that of conventional design. Performing DCT computations using Vedic multiplication sutras gives a significant performance even compared to a DCT using conventional. To illustrate our approach, the sample code implements part of JPEG compression routine, performs forward DCT on 8x8 blocks, quantizes coefficients, and performs inverse DCT.
References
- N. Ahmed, T. Natarajan, and K. R. Rao, "Discrete cosine transforms, IEEE Trans. Comput. , vol. 23, pp. 90–93, Jan. 1974. "
- Thuyen Le and Manfred Glesner," Flexible Architectures for DCT of Variable-Length Targeting Shape-Adaptive Transform", IEEE Transactions on Circuits and Systems For Video Technology, VOL. 10, NO. 8, December 2000.
- Liu Yuejun, Su Jing and Liu Feng ," Research on Information Hiding System based on DCT Domain", 2010 Second International Conference on Computer Modeling and Simulation, 978-0-7695-3941-6/10 IEEE, DOI10. 1109/ICCMS. 2010. 342, 2010.
- Jie Liang and Trac D. Tran," Fast Multiplierless Approximation of the DCT with the Lifting Scheme", IEEE Transaction on Signal Processing, Submitted; FEB. 2001.
- Nathaniel August and Dong Sam Ha, "On The Low-Power Design Of DCT and IDCT For Low Bit-Rate Video Codecs", Arlington, Virginia, Int. ASIC/SOC Conference,pp. 203-207, September 2001.
- Clay Gloster, Jr. , Wanda Gay, Michaela Amoo, and Mohamed Chouikha," Optimizing the Design of a Configurable Digital Signal Processor for Accelerated Execution of the 2-D Discrete Cosine Transform", Proceedings of the 39th Hawaii International Conference on System Sciences – 2006.
- Jagadguru Swami Sri Bharath, Krsna Tirathji, "Vedic Mathematics or Sixteen Simple Sutras From The Vedas", Motilal Banarsidas, Varanasi (India), 1986.
- "A Reduced-Bit Multiplication Algorithm For Digital Arithmetic" Harpreet Singh Dhilon And Abhijit Mitra, International Journal of Computational and Mathematical Sciences, Waset, Spring, 2008.
- Anvesh kumar,Ashish Raman,R K Sarin,Arun Khosla "Small Area Reconfigurable FFT Design by Vedic Mathematics " in Proc IEEE ICAAE'10,Singapoure, vol 5,pp. 836-838,Feb. 2010
- Shripad Kulkarni, "Discrete Fourier Transform (DFT) by using Vedic Mathematics"Papers on implementation of DSP algorithms/VLSI structures using Vedic Mathematics, 2006, www. edaindia. com, IC Design portal.
- "Lifting Scheme Discrete Wavelet Transform Using Vertical and Crosswise Multipliers" Anthony O'Brien and Richard Conway, ISSC, 2008, Galway, June 18-19.
- S. G. Dani, Vedic Maths': facts and myths, One India One People, Vol 4/6, January 2001, pp. 20-21; (available on www. math. tifr. res. in/ dani). 2008.
Index Terms
Keywords