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Reseach Article

A Novel Scaling Free Vectoring CORDIC and its FPGA Implementation

by Anita Jain, Kavita Khare, Supriya Aggarwal
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 63 - Number 14
Year of Publication: 2013
Authors: Anita Jain, Kavita Khare, Supriya Aggarwal
10.5120/10531-5521

Anita Jain, Kavita Khare, Supriya Aggarwal . A Novel Scaling Free Vectoring CORDIC and its FPGA Implementation. International Journal of Computer Applications. 63, 14 ( February 2013), 1-5. DOI=10.5120/10531-5521

@article{ 10.5120/10531-5521,
author = { Anita Jain, Kavita Khare, Supriya Aggarwal },
title = { A Novel Scaling Free Vectoring CORDIC and its FPGA Implementation },
journal = { International Journal of Computer Applications },
issue_date = { February 2013 },
volume = { 63 },
number = { 14 },
month = { February },
year = { 2013 },
issn = { 0975-8887 },
pages = { 1-5 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume63/number14/10531-5521/ },
doi = { 10.5120/10531-5521 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:14:18.658322+05:30
%A Anita Jain
%A Kavita Khare
%A Supriya Aggarwal
%T A Novel Scaling Free Vectoring CORDIC and its FPGA Implementation
%J International Journal of Computer Applications
%@ 0975-8887
%V 63
%N 14
%P 1-5
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This research paper proposes a novel scaling free CORDIC algorithm to operate in vectoring mode which computes absolute magnitude and phase angle of input vector. Using this algorithm, the micro rotation of the vector is unidirectional and totally scaling free. The range of convergence is successfully extended to cover entire coordinate space without increasing any hardware complexity. Further a 16 bit Scaling free vectoring CORDIC architecture based on this proposed algorithm is synthesized on FPGA Xilinx Virtex-5 device using Verilog hardware description language. Synthesized results show throughput every clock cycle with maximum operating frequency of 243. 55MHz and demonstrate very low dynamic power consumption.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Vectoring CORDIC Scaling free Quadrant Mapping Sectors Range of convergence ROC Pipeline architecture.