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Different Parameter Analysis of CMOS Charge Sharing Latch Comparator using 90nm Technology

by Ajay Vishwakarma, Sweta Sahu, Vijay Vishwakarma, Richa Soni
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 63 - Number 11
Year of Publication: 2013
Authors: Ajay Vishwakarma, Sweta Sahu, Vijay Vishwakarma, Richa Soni
10.5120/10507-5381

Ajay Vishwakarma, Sweta Sahu, Vijay Vishwakarma, Richa Soni . Different Parameter Analysis of CMOS Charge Sharing Latch Comparator using 90nm Technology. International Journal of Computer Applications. 63, 11 ( February 2013), 1-6. DOI=10.5120/10507-5381

@article{ 10.5120/10507-5381,
author = { Ajay Vishwakarma, Sweta Sahu, Vijay Vishwakarma, Richa Soni },
title = { Different Parameter Analysis of CMOS Charge Sharing Latch Comparator using 90nm Technology },
journal = { International Journal of Computer Applications },
issue_date = { February 2013 },
volume = { 63 },
number = { 11 },
month = { February },
year = { 2013 },
issn = { 0975-8887 },
pages = { 1-6 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume63/number11/10507-5381/ },
doi = { 10.5120/10507-5381 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:15:09.891780+05:30
%A Ajay Vishwakarma
%A Sweta Sahu
%A Vijay Vishwakarma
%A Richa Soni
%T Different Parameter Analysis of CMOS Charge Sharing Latch Comparator using 90nm Technology
%J International Journal of Computer Applications
%@ 0975-8887
%V 63
%N 11
%P 1-6
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In the present works, mainly power consumption of circuit is main issue for every designers. This paper mainly dealing with the implementation of CMOS Charge sharing latch Comparator and analysis of it using different parameter in 90nm. For the implementation of new design the features of two important Comparator are combined so that the power dissipation is reduced and speed of new design is increased. These two Comparator are Resistive Dividing Comparator and Differential Current sensing respectively. The simulation result is shown in 90nm technologies, for 2. 4GHz clocked comparator by using 0. 9V input. Again the result of 90nm technology is compared with 180nm technology to show the reduction of power and enhancement of speed. The implementation is done on the Cadence virtuoso design environment.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Power analysis CMOS latch comparators

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