We apologize for a recent technical issue with our email system, which temporarily affected account activations. Accounts have now been activated. Authors may proceed with paper submissions. PhDFocusTM
CFP last date
20 November 2024
Reseach Article

Survey on FPGA-based Pipelined Architecture for RC5 Encryption

by Ashmi Singh, Puran Gour, Brij Bihari Soni
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 62 - Number 4
Year of Publication: 2013
Authors: Ashmi Singh, Puran Gour, Brij Bihari Soni
10.5120/10069-4679

Ashmi Singh, Puran Gour, Brij Bihari Soni . Survey on FPGA-based Pipelined Architecture for RC5 Encryption. International Journal of Computer Applications. 62, 4 ( January 2013), 28-31. DOI=10.5120/10069-4679

@article{ 10.5120/10069-4679,
author = { Ashmi Singh, Puran Gour, Brij Bihari Soni },
title = { Survey on FPGA-based Pipelined Architecture for RC5 Encryption },
journal = { International Journal of Computer Applications },
issue_date = { January 2013 },
volume = { 62 },
number = { 4 },
month = { January },
year = { 2013 },
issn = { 0975-8887 },
pages = { 28-31 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume62/number4/10069-4679/ },
doi = { 10.5120/10069-4679 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:10:48.098631+05:30
%A Ashmi Singh
%A Puran Gour
%A Brij Bihari Soni
%T Survey on FPGA-based Pipelined Architecture for RC5 Encryption
%J International Journal of Computer Applications
%@ 0975-8887
%V 62
%N 4
%P 28-31
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In current scenario, electronic devices handling confidential information. In these devices encryption algorithm proposed have been satisfy to protect the confidential information and known for their cryptographic applications. The extensively use of reconfigurable processor like FPGA for cryptographic application which have reduced the time to market of hardware logic. In this survey presented that the FPGA-based hardware architecture is best approach for high performance of circuit, it reduces the response time and resources. This hardware architecture work on Verilog as well as VHDL language.

References
  1. Masaya Y. , and K. Sakaun 2011. "Dedicated hardware for RC5 cryptography and its Implementation".
  2. Zhigang wu and Wei wang, 2011. "Pipelined Architecture for FPGA Implementation of Lifting-Based DWT".
  3. Chengjun Z. Chuyan W. , and M. omair Ahmad, 2012. "A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform".
  4. A. Ruhan Bevi1, S. S. V. Sheshu, and S. Malarvizhi"2012. FPGA based Sliding Window Architecture for RC5 Encryption".
  5. A. Ruhan Bevi1, S. S. V. Sheshu, and S. Malarvizhi 2012. "FPGA based Pipelined Architecture for RC5 Encryption".
  6. K El-latif, 2010. "Hardware Implemented of DES using Pipelining Concept with Time-Variable Key". 22nd International Conference on Microelectronics (ICM), Egypt.
  7. A. Klimm, M. Haas, O. Sander, and J. Becker, 2010. "A flexible integrated crypto processor for authentication protocols based on hyper elliptic curve cryptography", Proc. of International Symposium on System on Chip (SoC), pp. 35-42,
  8. A. Irwansyah, V. P. Nambiar, and M. Khalil-Hani 2009. "An AES Tightly Coupled Hardware Accelerator in an FPGA-based Embedded Processor Core". pp. 521-525
  9. B. B. Brumley, and K. U. Jarvinen, 2010. "Conversion Algorithms and Implementations for Koblitz Curve Cryptography". pp. 81-92
  10. M. Rahman, I. R. and Rokon, 2009. "Efficient hardware implementation of RSA cryptography", Proc. of International Conference on Anti-counterfeiting, Security, and Identification in Communication, pp. 316-319.
  11. F. A. G. Muzzi, R. B. Chiaramonte, and E. D. M. Ordonez, 2009. "The Hardware-based PKCS#11 Standard using the RSA Algorithm", pp. 160-169.
  12. Zhang Lina, 2010. "Research on critical technology of elliptic curve cryptosystem SOC". Proc. of International Conference on Communication Systems, Networks and Applications. pp. 77. 80.
  13. Zhimin Chen, P. Schaumont, "Early feedback on side channel risks with accelerated toggle-counting", Proc . of IEEE International Workshop on Hardware-Oriented Security and Trust, pp. 90-95.
  14. Juha Kukkurainen, Mikael Soini, and Lauri Sydanheimo, 2010. "RC5-Based Security in Wireless Sensor Networks: Utilization and Performance".
  15. Yain-Reu Lin; Chia-Hao Hsu; Rieger, and R. ; Chua-Chin Wang, "Low power RC5 cipher for ZigBee portable biomedical systems", pp 615 – 616.
  16. Dhanashri H. Gawali and Vijay M. Wadhai, 2012. "RC5 algorithm: potential cipher solution for security in wireless body sensor networks"
Index Terms

Computer Science
Information Sciences

Keywords

FPGA RC5 Pipeline