The week's pick
Reseach Article
Hardware Implementation of DSP Filter on FPGAs
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 62 - Number 16 |
| Year of Publication: 2013 |
| Authors: Apurva Singh Chauhan, A. Mukund Lal, Varun Maheshwari, D. Bhagwan Das |
10.5120/10167-4969
|
Apurva Singh Chauhan, A. Mukund Lal, Varun Maheshwari, D. Bhagwan Das . Hardware Implementation of DSP Filter on FPGAs. International Journal of Computer Applications. 62, 16 ( January 2013), 34-37. DOI=10.5120/10167-4969
Abstract
This paper describes the hardware implemention of Digital signal processing filters on FPGAs (Field programmable gate array). Traditionally, digital signal processing (DSP) algorithms are implemented using general purpose programmable DSP chips for low-rate applications. Alternatively, special purpose fixed function DSP chipsets and application specific integrated circuits (ASICs) are used for high-performance application. Technological amelioration by Xilinx on FPGAs in the past few years has opened new paths for engineers to design various applications on FPGAs. The FPGAs assert the high explicitness of the ASIC while avoiding its high development cost and its inability to accommodate design modifications after production. Highly adaptable and design-flexibility, FPGAs provide optimal device utilization through conservation of board space and system power important advantages not available with many stand-alone DSP chips.
References
- Ray Goslin, Dr. San Jose, CA 95124 A Guide to Using Field Programmable Gate Arrays (FPGAs) for Application-Specific Digital Signal Processing Performance Gregory Digital Signal Processing Program Manager Xilinx, Inc. 2100 Logic .
- Mark S. Manalo and Ashkan Ashrafi "Implementing Filters on FPGAs" Department of Electrical and Computer Engineering Real-Time DSP and FPGA Development Lab
- Prabhat Ranjan(July 2008) "Implementation of FIR Filter on FPGA"Department of Electronics and Communication Thapar University,Punjab
- Joseph B. Evans "An Efficient FIR Filter Architecture" Telecommunications & Information Sciences Laboratory Department of Electrical & Computer Engineering University of Kansas Lawrence, KS 66045-2228
- D. E. Borth, I. A. Gerson, J. R. Haug, and C. D. Thompson (Apr 1988). A flexible adaptive FIR filter VLSI IC. IEEE Journ. Select. Areas Commun. , SAC-6(3):494–503,.
- P. R. Cappello, editor 1984. VLSI Signal Processing. IEEE Press,
- J. B. Evans,Y. C. Lim, and B. Liu. ( Apr 1990) A high speed programmable digital FIR filter. In IEEE Int. Conf. Acoust. , Speech, Signal Processing,
- J. Gallia et al (Feb 1990). High-performance BiCMOS 100k-gate array. IEEE J. Solid State Circuits, SC-25(1):142–149.
- R. Hartley, P. Corbett, P. Jacob, and S. Karr. , May 1989 A high speed FIR filter designed by compiler. In IEEE Cust. IC Conf. , pages 20. 2. 1–20. 2. 4.
- R. Rabiner1 and Ronald W. Schafer2 Introduction to Digital Speech Processing Lawrence 1 Rutgers University and University of California, Santa Barbara, USA, rabiner@ece. ucsb. edu 2 Hewlett-Packard Laboratories, Palo Alto, CA, USA
- NITSCHKE and GREGORY A. MILLER Digital filtering in EEG/ERP analysis: Some technical and empirical comparisons ACK B. university of Illinois at Urbana-Champaign, Urbana, Illinois and EDWIN W. COOK III University of Alabama, Birmingham, Alabama
- R. Boite and H. Leich,comments in (1984. ) on 'A fast procedure to design equirriple minimum phase Fir filters. 'IEEE Trans. Circuits Syst. CAS-31,503-504
- FPGA Architect - XilinxXC4000/Spartan. By ELANIX Inc.
- Spartan-3 Starter Kit Board User Guide UG130 (v1. 1) May 13, 2005
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