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Design and Simulation of Low power CMOS Adder Cell at 180nm using Tanner Tool

by Chakshu Goel, Puneet Jain, Gurjeevan Singh
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 62 - Number 16
Year of Publication: 2013
Authors: Chakshu Goel, Puneet Jain, Gurjeevan Singh
10.5120/10166-4958

Chakshu Goel, Puneet Jain, Gurjeevan Singh . Design and Simulation of Low power CMOS Adder Cell at 180nm using Tanner Tool. International Journal of Computer Applications. 62, 16 ( January 2013), 30-33. DOI=10.5120/10166-4958

@article{ 10.5120/10166-4958,
author = { Chakshu Goel, Puneet Jain, Gurjeevan Singh },
title = { Design and Simulation of Low power CMOS Adder Cell at 180nm using Tanner Tool },
journal = { International Journal of Computer Applications },
issue_date = { January 2013 },
volume = { 62 },
number = { 16 },
month = { January },
year = { 2013 },
issn = { 0975-8887 },
pages = { 30-33 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume62/number16/10166-4958/ },
doi = { 10.5120/10166-4958 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:12:00.467120+05:30
%A Chakshu Goel
%A Puneet Jain
%A Gurjeevan Singh
%T Design and Simulation of Low power CMOS Adder Cell at 180nm using Tanner Tool
%J International Journal of Computer Applications
%@ 0975-8887
%V 62
%N 16
%P 30-33
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this Research Paper, the focus is on the analysis and simulation of the Adder cell which is slightly different as compared to the existing circuits and optimized for Average Power Dissipation. In this paper the adder cell is modified circuit in such a way that it controls the overall capacitances during the Sum and Carry evaluation and will optimize the total capacitance that results in the decrease of the Average Power dissipation. The circuit is characterized by using HSPICE in a 180 nanometer (nm) with supply voltage of 1. 8 volt and threshold voltage is 0. 40 volts.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Full Adder Tanner Tool CMOS circuit VLSI

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