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Implementation of Scheduling Algorithms for On Chip Communications
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 62 - Number 14 |
| Year of Publication: 2013 |
| Authors: U. Saravanakumar, K. Rajasekar, R. Rangarajan |
10.5120/10151-4986
|
U. Saravanakumar, K. Rajasekar, R. Rangarajan . Implementation of Scheduling Algorithms for On Chip Communications. International Journal of Computer Applications. 62, 14 ( January 2013), 35-38. DOI=10.5120/10151-4986
Abstract
Network on Chips (NoCs) replace traditional busses in highly integrated Multiprocessor System on Chips (MPSoCs). As SoCs, communication issues take much important in NoCs but they need to give contention free architecture with low latency. To meet the above need several methods like handshaking mechanism and arbiter designs developed and implemented. This paper presents various scheduler designs using iSLIP scheduling algorithms and its comparative analysis with various arbiters. All the arbiters described using Verilog HDL and synthesized using Xilinx. For performance analysis, Cadence RTL compiler with UMC 0. 13µm technology used to compute power and area of all the algorithms for arbiter.
References
- International Technology Roadmap for Semiconductors. http://www. itrs. net/
- Tobias Bjerregaard and Shankar Mahadevan. "A survey of research and practices of network-on-chip", ACM Computing Surveys, 38(1), 2006.
- William J. Dally and Brian Towles. Route Packets, Not Wires: On-Chip Interconnection Networks. In Proc. of the 38th Design Automation Conference (DAC), June 2001.
- W. J. Dally. Wire-Efficient VLSI Multiprocessor Communication Networks. In Paul Losleben, editor, Proceedings of the Stanford Conference on Advanced Research in VLSI. MIT Press, March 1987.
- William J. Dally and Brian Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann, 2003.
- Zhizhou Fu; Xiang Ling, The design and implementation of arbiters for Network-on-chips, Industrial and Information Systems (IIS), 2010 2nd International Conference on , vol. 1, no. , pp. 292-295, 10-11 July 2010.
- Yun-Lung Lee; Jer Min Jou; Yen-Yu Chen, A high-speed and decentralized arbiter design for NoC, Computer Systems and Applications, 2009. AICCSA 2009. IEEE/ACS International Conference on , vol. , no. , pp. 350-353, 10-13 May 2009.
- Eung S. Shin, Vincent J. Mooney III and George F. Riley, Round-robin Arbiter Design and Generation, ISSS'02, Japan, 2002.
- Baranowska, A. ; Kabacinski, W, Hierarchical round-robin matching for virtual output queuing switches, Telecommunications, 2005. advanced industrial conference on telecommunications/service assurance with partial and intermittent resources conference/e-learning on telecommunications workshop. aict/sapir/elete 2005. Proceedings, vol. , no. , pp. 196- 201, 17-20 July 2005.
- Minagar, A. R. ; Safavi, S. M, The optimized prioritized iSLIP scheduling algorithm for input-queued switches with ability to support multiple priority levels, Telecommunications, 2003. ICT 2003. 10th International Conference on, vol. 2, no. , pp. 1680- 1685 vol. 2, 23 Feb. -1 March 2003.
- N. McKeown, "The islip scheduling algorithm for input-queued switches," Networking, IEEE/ACM Transactions on, vol. 7, no. 2, pp. 188–201, Apr 1999.
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