The week's pick
Reseach Article
Implementation of Scheduling Algorithms for On Chip Communications
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 62 - Number 14 |
| Year of Publication: 2013 |
| Authors: U. Saravanakumar, K. Rajasekar, R. Rangarajan |
10.5120/10151-4986
|
U. Saravanakumar, K. Rajasekar, R. Rangarajan . Implementation of Scheduling Algorithms for On Chip Communications. International Journal of Computer Applications. 62, 14 ( January 2013), 35-38. DOI=10.5120/10151-4986
Abstract
Network on Chips (NoCs) replace traditional busses in highly integrated Multiprocessor System on Chips (MPSoCs). As SoCs, communication issues take much important in NoCs but they need to give contention free architecture with low latency. To meet the above need several methods like handshaking mechanism and arbiter designs developed and implemented. This paper presents various scheduler designs using iSLIP scheduling algorithms and its comparative analysis with various arbiters. All the arbiters described using Verilog HDL and synthesized using Xilinx. For performance analysis, Cadence RTL compiler with UMC 0. 13µm technology used to compute power and area of all the algorithms for arbiter.
References
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