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Charge Redistribution based 8 bit SAR ADC
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 62 - Number 1 |
| Year of Publication: 2013 |
| Authors: Vijay V, Bhavya R, Vipula Singh |
10.5120/10042-4625
|
Vijay V, Bhavya R, Vipula Singh . Charge Redistribution based 8 bit SAR ADC. International Journal of Computer Applications. 62, 1 ( January 2013), 6-9. DOI=10.5120/10042-4625
Abstract
An 8-bit 10 MS/s SAR A/D converter is presented. In the circuit design, a capacitor switched D/A Converter architecture, Dynamic latched comparator architecture and low power SAR logic are utilized. Design challenges and considerations are also discussed. This proposed converter is implemented based on 0. 29um CMOS logic process. With a 3. 3 V analog supply and a 5 V digital supply, the differential and integral nonlinearity are measured to be less than 0. 36 LSB and 0. 69 LSB respectively. With an input frequency of 625 KHz at 10 MS/s sampling rate and the power dissipation is measured to be 6. 62 mW.
References
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