An important issue in PLL design and manufacture is to simulate, measure, and verify its performance and key parameters for achieving goals of good time and frequency domain responses, as well as good noise and jitter performance. In this paper, we will introduce our new method that is capable of simulating and measuring automatically the PLL key parameters, such as the hold-in range and the pull-in range. Performance parameters for the PLL, such as loop gain, damping factor, natural frequency and settling time, can be simulated and measured concurrently. This method will help to shorten the time of measurements. This work presents an automatic testing method for the PLL using circuit simulator and practical circuit implementation. An industrial CMOS PLL is used to implement the PLL. Good agreement between the simulation and experimental is results is found.

Phase locked loop tracking range capture range natural frequency damping factor