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A New PWL Approximation for the "Self-Adjustable Offset Min-Sum" Decoding with a highly Reduced-Complexity

by Abdessalam Ait Madi, Anas Mansouri, Ali Ahaitouf
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 61 - Number 19
Year of Publication: 2013
Authors: Abdessalam Ait Madi, Anas Mansouri, Ali Ahaitouf
10.5120/10033-5068

Abdessalam Ait Madi, Anas Mansouri, Ali Ahaitouf . A New PWL Approximation for the "Self-Adjustable Offset Min-Sum" Decoding with a highly Reduced-Complexity. International Journal of Computer Applications. 61, 19 ( January 2013), 1-6. DOI=10.5120/10033-5068

@article{ 10.5120/10033-5068,
author = { Abdessalam Ait Madi, Anas Mansouri, Ali Ahaitouf },
title = { A New PWL Approximation for the "Self-Adjustable Offset Min-Sum" Decoding with a highly Reduced-Complexity },
journal = { International Journal of Computer Applications },
issue_date = { January 2013 },
volume = { 61 },
number = { 19 },
month = { January },
year = { 2013 },
issn = { 0975-8887 },
pages = { 1-6 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume61/number19/10033-5068/ },
doi = { 10.5120/10033-5068 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:09:50.351726+05:30
%A Abdessalam Ait Madi
%A Anas Mansouri
%A Ali Ahaitouf
%T A New PWL Approximation for the "Self-Adjustable Offset Min-Sum" Decoding with a highly Reduced-Complexity
%J International Journal of Computer Applications
%@ 0975-8887
%V 61
%N 19
%P 1-6
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

A new PieceWiseLinear (PWL) function is proposed for the decoding of the Low-Density-Parity-Check (LDPC) code with the Self Adjustable Offset Min-Sum (SAOMS) algorithm. Avoiding the use of the non-linear function f(x) = ln ?? 1 + e??jxj in the adjustable offset factor, this linear approximation greatly simplifies the hardware implementation with a little BER performance loss. The proposed solution is new, useful and is successfully tested on decoding regulars (504, 252) and (8000, 4000) LDPC codes. The corresponding Check Node Processing Unit (CNPU) have been designed, described and simulated using Very High Speed integrated circuits Hardware Description language(VHDL). The synthesis results were obtained using an Altera Quartus II software with cyclone II EP2CF896C6 as the target FPGA device. The designed CNPU is fully parallel and flexible to be used for different block length when a regulars (3, 6) LDPC codes are required.

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Index Terms

Computer Science
Information Sciences

Keywords

LDPC BER FPGA BP PWL VHDLifx

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