The week's pick
Random Articles
Reseach Article
Conditional Precharge Dynamic Buffer Circuit
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 60 - Number 6 |
| Year of Publication: 2012 |
| Authors: Amit Kumar Pandey, Vivek Mishra, Ram Awadh Mishra, Rajendra Kumar Nagaria, V. Krishna Rao Kandanvli |
10.5120/9699-4141
|
Amit Kumar Pandey, Vivek Mishra, Ram Awadh Mishra, Rajendra Kumar Nagaria, V. Krishna Rao Kandanvli . Conditional Precharge Dynamic Buffer Circuit. International Journal of Computer Applications. 60, 6 ( December 2012), 45-52. DOI=10.5120/9699-4141
Abstract
In this paper, footless domino logic buffer circuit is proposed. It minimizes redundant switching at the dynamic and the output nodes. This circuit passes propagation of precharge pulse to the dynamic node and avoids precharge pulse to the output node which saves power consumption. Simulation is done using 0. 18µm CMOS technology. We have calculated the power consumption, delay and power delay product of proposed circuit and compared the results with existing circuits for different logic function, loading condition, clock frequency, temperature and power supply. For capacitance 500fF, our proposed circuit reduces power consumption by 72. 69%, 26. 35% and 24. 03% as compared to standard footless domino, SP-Domino and SSPD techniques.
References
- Wei. H, Josji. R. H and Henkels, 1999, "a 500-Mhz, 32-word, a 64 bit, eight-port self-resetting CMOS register file", IEEE Tranactions on Solid-State Circuits, pp. 56-67.
- Nowka. K. J and Galambos. T, 1998, "Circuit design techniques for a gigahertz integer microprocessor", IEEE International Conference on Computer Design, pp. 11-16.
- Agrawal. A. K, Wairya. S, Nagaria. R. K,Tiwari. S, 2009, "Mixed gate diffusion input full adder topology for high speed low power digital circuits", World Applied Sciences Journal (WASJ:Special Issue of Computer & IT), IDOSI Publication,vol. 7,pp. 138-144.
- Krambeck. R. H, Lee. C. M, and Law. H, 1982, "High-speed compact circuits with CMOS", IEEE Journal of Solid-State Circuits, vol. SC-17, no. 3, pp. 614-619.
- Thorp. T, Dean. L and Trivedi. P, 2003, "Analysis of blocking dynamic circuits", IEEE Transactions on VLSI Systems, pp. 744-749.
- Charbel. J. A and Magdy. A. B, 2008, "Single-phase SP –domino:A limited-switching dynamic circuit technique for low-power wide fan-in logic gates ", IEEE Transactions on Circuits and Systems, vol. 55,no. 2, pp. 141-145.
- Singh. R, Moon. G, Kim. M, Park. J, W, Shin. W. Y and Kim. S, 2012, "Static-switching pulse domino: A switching-aware design technique for wide fan-in dynamic multiplexers", Integratiom, The VLSI Journal, vol. 45, pp. 253-262.
- Tang. T and Bermak . A, 2012, "Low power TSPC-based domino logic circuit design with 2/3 clock load", Transactions on Energy Procedia, vol. 14, pp. 1168-1174.
- Ren. Y. J. , Karlsson. J and Svensson, 1987, "A true single-phase clock dynamic CMOS circuit technique", IEEE Transactions on Solid-State Circuits, vol. 22, no. 5, pp. 899-901.
- Jayakumaran. S, Hung. C. N, Kevin. J. N, Robert. K and Brown. B, 2005, "Controlled-load limited switch dynamic logic circuit", IEEE Conference on Computer Society, pp. 1-6.
- Fang. T, Amine. B and Zhouye. G, 2012, "Low power dynamic logic circuit design using a pseudo dynamic buffer", Integration, the VLSI journal, vol. 45, pp. 395-404.
- Berkeley Predictive Technology Model (BPTM), http:// www. device. eecs. berkeley. edu/wptm/ download. htm.
- Yee. G, Sechen. C, 2000, "Clock-delayed domino for dynamic circuit design", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, pp. 425-430.
Index Terms
Keywords