The week's pick
Random Articles
Reseach Article
Performance Analysis of CNFET based Interconnect Drivers for Sub-threshold Circuits
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 60 - Number 4 |
| Year of Publication: 2012 |
| Authors: S. S. Chopade, S. D. Pable, Dinesh V Padole |
10.5120/9680-4109
|
S. S. Chopade, S. D. Pable, Dinesh V Padole . Performance Analysis of CNFET based Interconnect Drivers for Sub-threshold Circuits. International Journal of Computer Applications. 60, 4 ( December 2012), 16-19. DOI=10.5120/9680-4109
Abstract
Subthreshold VLSI circuits design received ample interest due to rapid growth of portable devices. The portable domain places in flexible limitation on the power dissipation. Though, device operating in subthreshold region shows huge potential towards satisfying the ultra low power requirement, it holds lots of difficult design issues. As integration density of interconnects increases at every technology node, increased delay and crosstalk effects may comes a more challenging design problem particularly for subthreshold interconnects. Nanometer subthreshold global interconnect faces subthreshold driver design challenges and problems due to increased interconnect capacitance. This paper examined use of CNFET based interconnect driver even for ultra low power circuits and compared the performance with Si-MOSFET based interconnect driver. It has been reported that CNFET driver provides 9. 74 times lower EDP over Si-MOSFET based driver. It also reported better combination of number of tubes, inter CNT pitch and tube diameter for lower delay and EDP.
References
- N. S. Kim, K. Flautner, D. Blaauw, and T. Mudge, "Circuit and micro archirectural techniques for reducing cache leakage power," IEEE Transactions on Very Large Scale Integration (VLSI) System, Vol. 12. No. 2, pp. 167-187, 2004.
- J. M. Rabaey, A. P. Chandrakasan, and B. Nikolic, Digital Integrated Circuits- A Design Perspective, 2nd Edition, Prentice Hall, New Jersey,USA, 2003.
- A. Wang, B. H. Calhoun, A. P. Chandrakasan, Sub-Threshold Design for Ultra Low-Power Systems, first ed. , Springer, New York, 2006.
- B. H. Calhoun, J. F. Ryan, S. Khanna, M. Putic, and J. Lach, "Flexible circuits and architecture for ultra low power," Proceeding of the IEEE, Vol. 98, No. 2, pp. 267-282, Jan. 2010.
- A. Tajalli and Y. Leblebici, Extreme Low –Power Mixed Signal IC Design- Subthreshold Source –Coupled Circuits, 1st ed. , Springer, New York, 2010.
- S. Hanson, M. Seok, D. Sylvester, and D. Blaauw, "Nanometer device scaling in subthreshold logic and SRAM," IEEE Trans. on Electron Devices, Vol. 55, No. 1, pp. 175-185, Jan. 2008.
- F. Chen, A. Joshi, V. Stojanovic, and A. P. Chandrakasan, "Scaling and evaluation of carbon nanotube interconnects for VLSI applications," Nano-Net, Sept. 2007.
- Predictive Technology Model, Available : http://www. eas. asu. edu/ptm/
- ITRS, International Technology Roadmap for semiconductors, 2005.
- J. Deng and A. Wang, "A compack SPICE model for carbon –nanotube field-effect transistors including nonidealities and its application- Part I: Model of the intrinsic channel region," IEEE Transactions on Electron Devices, Vol. 54, No. 12, pp. 3186-3194, Dec. 2007.
- Stanford University CNFET Model Web site, (2008). [Online]. Available: http: //nano. stanford. edu/model. php?id=23
- H. S. P. Wong, J. Deng, A. Hazeghi, T. Krishnamohan, and G. C. Wan, "Carbon nanotubes transistor circuits-models and tools for design and performance optimization," in Proceeding of International Conference on Computer Aided Design (ICCAD), pp. 651-654, Nov. 2006.
Index Terms
Keywords