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Logic Circuit Design Implementation on FPGA at Reduced Dynamic Power Consumption
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 60 - Number 19 |
| Year of Publication: 2012 |
| Authors: Kirthika Anandan, Kishana R. Kashwan |
10.5120/9811-4420
|
Kirthika Anandan, Kishana R. Kashwan . Logic Circuit Design Implementation on FPGA at Reduced Dynamic Power Consumption. International Journal of Computer Applications. 60, 19 ( December 2012), 43-49. DOI=10.5120/9811-4420
Abstract
This paper introduces a new technique for reducing glitches in logic circuits implemented on Field Programmable Gate Arrays (FPGAs). The technique is based on the principles of path balancing. The main objective was to achieve glitch minimization which, in turn would reduce dynamic power during routing on FPGAs. The glitch aware routing was adopted for simulations tests. The input paths to look-up table (LUT) are balanced by aligning signals so that all input signals arrive simultaneously at LUT. To perform simulation tests and validation of new design, two different benchmark logic circuits of adder and multiplier were considered for implementation on FPGAs. Simulated results' analyses of selected benchmark circuits showed that there was a reduction in dynamic power consumption by FPGAs by about 11. 5% and 7. 5% for LUT input size of 16 bits, for adder and multiplier circuits respectively. The improvements in power consumptions are based on the computations for glitch aware router with path balancing compared to that of glitch unaware routers.
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