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An Analysis of Power and Stability in 6T, NC, Asymmetric, PP, and P3SRAM Bit-Cells Topologies in 45nm CMOS Technology
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 59 - Number 3 |
| Year of Publication: 2012 |
| Authors: Madhurima Kumar, Anshul Arora, Ritu Arora, Neeraj Kr. Shukla, P. Bhatnagar, S. Birla |
10.5120/9529-3953
|
Madhurima Kumar, Anshul Arora, Ritu Arora, Neeraj Kr. Shukla, P. Bhatnagar, S. Birla . An Analysis of Power and Stability in 6T, NC, Asymmetric, PP, and P3SRAM Bit-Cells Topologies in 45nm CMOS Technology. International Journal of Computer Applications. 59, 3 ( December 2012), 18-21. DOI=10.5120/9529-3953
Abstract
In modern digital architectures, more and more emphasis has been laid on increasing the number of SRAMs in a SoC. However, with the increase in the number of SRAMs, the power requirement also increases, which is not desired. This calls for an urgent need for an SRAM with low dynamic and static power consumption and stability at the same time. The design and simulation work for 6T-SRAM, NC-SRAM, Asymmetric SRAM, PP-SRAM, and P3-SRAM topologies have been carried out to see their power consumption and performance at 45nm CMOS technology at 300oK for VDD=0. 7V and 0. 8V. At VDD=0. 8V, P3-SRAM consumes 69. 069%, 13. 61%, 82. 03% and 86. 11% less standby power than 6T-SRAM, NC-SRAM, Asymmetric SRAM and PP-SRAM, respectively. Similarly, the dynamic power consumed by P3-SRAM is 88. 88%, 89. 23%, 85. 25% and 89. 5% less than 6T-SRAM, NC-SRAM, Asymmetric SRAM and PP-SRAM, respectively at VDD=0. 8V.
References
- K. Zhang (Ed. ), "Embedded Memories for Nano-Scale VLSIs," Integrated Circuits and Systems Series, Springer, 2009.
- E. J. Marinissen, B. Prince, and D. K. S. Y. Zorian, "Challenges in embedded memory design and test", in Proceedings of Design, Automation, and Test in Europe Conference and Exhibition, pp. 722-727, Mar. 2005.
- G. Gray, S. Borkar, and V. De, "Life is CMOS: Why Chase Life After?",Proc. IEEE Des. Autom. , Conf. , pp. 78-83, Jun. , 2002.
- V. Kursun, E. G. Friedman, "Multi-Voltage CMOS Circuit Design", New York: Wiley 2006.
- G. Razavipour, A. Afzali-Kusha, and M. Pedram, "Design and Analysis of Two Low-PowerSRAM Cell Structures", IEEE transactions on Very Large Scale Integration (VLSI) Systems, VOL. 17, NO. 10, October 2009.
- Rakesh Kumar Singh, ManishaPattanaik, Neeraj Kr. Shukla, "Characterization of a Novel Low-Power SRAM Bit-Cell Structure at Deep Sub-Micron CMOS Technology for Multimedia Applications", Circuits and Systems, 2012, 3, 23-28.
- N. Azizi and F. N. Najm, "An asymmetric SRAM cell to lower gate leakage," in Proc. 5th IEEE Int. Symp. Quality Electron. Design, 2004, pp. 534–539.
- P. Elakkumanan, C. Thondapu, and R. Sridhar, "A gate leakagereduction strategy for Sub-70 nm memory circuit," in Proc. IEEEDallas/CAS Workshop, 2004, pp. 145–148.
- B. Amelifard, F. Fallah, and M. Pedram, "Reducing the sub-thresholdand gate-tunneling leakage of SRAM cells using dual-Vt and dual-Toxassignment," in Proc. DATE, Mar. 2006, pp. 1–6.
- Jan. M. Rabaey, AnathaChandrakasan, BorivojeNikolic, "Digital Integrated Circuits: A Design Perspective," Second Ediiton, PHI Learning Private Limited, New Delhi, 2009.
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