The week's pick
Reseach Article
A Low Power 90nm Technology based CMOS Digital Gates with Dual Threshold Transistor Stacking Technique
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 59 - Number 11 |
| Year of Publication: 2012 |
| Authors: P. S. Aswale, S. S. Chopade |
10.5120/9596-4215
|
P. S. Aswale, S. S. Chopade . A Low Power 90nm Technology based CMOS Digital Gates with Dual Threshold Transistor Stacking Technique. International Journal of Computer Applications. 59, 11 ( December 2012), 47-52. DOI=10.5120/9596-4215
Abstract
Scaling of transistor features sizes has improves performance, increase transistor density and reduces the power consumption. A chip's maximum power consumption depends on its technology as well as its implementation. As technology scales down and CMOS circuits are powered by lower supply voltages, leakage current becomes significant. static power is becoming the predominant source of energy waste. To create methodologies that support efficient designs, good performance, lower costs in the era of low power, is up to the design, EDA community . As the threshold voltage is reduced due to scaling, it leads to increase in sub threshold leakage current and hence increase in static power dissipation. This paper presents performance analysis of inverter using conventional CMOS, stack and dual threshold transistor stacking techniques. The performance analysis of inverter were analyzed in 90nm technology using Cadence virtuoso environment. The use of dual threshold voltages can significantly reduce static power dissipated in CMOS VLSI circuits.
References
- R. Udaiyakumar, K. Sankaranarayanan, "Dual Threshold Transistor Stacking (DTTS) - A Novel Technique for Static Power Reduction in Nanoscale Cmos Circuits', European Journal of Scientific Research, ISSN 1450-216X Vol. 72 No. 2 (2012), pp. 184-194.
- Jagannath Samanta, Bishnu Prasad De, Banibrata Bag, Raj Kumar Maity, " Comparative study for delay & power dissipation of CMOS Inverter in UDSM range", International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-1, Issue-6, January 2012.
- Jun Cheol Park and Vincent J. Mooney III," Sleepy Stack Leakage Reduction", IEEE transactions on very large scale integration (VLSI) SYSTEMS, VOL. 14, NO. 11, November 2006.
- Neil Weste, Harris, Banerjee, " CMOS VLSI Design, a circuit and system Perspective". .
- Sung-Mo Kang and Yusuf Leblebici, "CMOS Digital Integrated Circuits Analysis and Design".
- Chuck Hawkins and Jaume Segura, "Introduction to Digital Electronics".
- International Technology Roadmap for Semiconductors by Semiconductor Industry Association, 2009. [Online]. Available http://public. itrs. net.
- Gerson Scartezzini, Ricardo Reis, "Using Transistor Networks to Reduce Static Power in CMOS Circuits", SIM 2011 - 26th South Symposium on Microelectronics.
- Cadence Design Systems, http://www. cadence. com/.
- R. Udaiyakumar , K. Sankaranarayanan, " Certain Investigations on Static Power Dissipation in various Nano-Scale CMOS D Flip-Flop Structures" , International Journal of Engineering and Technology Volume 2 No. 4, April, 2012.
- Bipul C. Paul, Amit Agarwal, Kaushik Roy,"Lowpower design techniques for scaled technologies", INTEGRATION, the VLSI journal 39 (2006) 6489.
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