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Parallel implementation of Multi-view Video Decoder for Reduction in Power Consumption
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 58 - Number 17 |
| Year of Publication: 2012 |
| Authors: Xiang Jun Zhao, Yeon-man Jeong, Yong Beom Cho |
10.5120/9374-3847
|
Xiang Jun Zhao, Yeon-man Jeong, Yong Beom Cho . Parallel implementation of Multi-view Video Decoder for Reduction in Power Consumption. International Journal of Computer Applications. 58, 17 ( November 2012), 23-26. DOI=10.5120/9374-3847
Abstract
Mobile platform based multi view video applications have gained significant attention due to increase in processing power of mobile processors. Significant performance improvements have been reported by using H. 264/AVC based video encoding-decoding procedures. Multi-view coding (MVC) is an extension of H. 264/AVC scheme employed for high performance compression of multi view videos. The increase in spatial/temporal information has increased the difficulties in real-time decoding. In existing implementations, multi-processor based architectures have been employed to achieve real-time processing in H. 264/AVC. In this paper, a parallel MVC decoding scheme is presented. The implementation is based on pipelined architecture of Cortex-A8 processor and graphics processing unit (GPU). The decoding procedure is divided into block based and pixel based operations. The GPU is employed for processing pixel based operations while the CPU performs the block based sequential operations. The implementation results shows that the proposed scheme can achieve same peak signal-to-noise ratio (PSNR) performance with more than 29% increase in decoding speed. Hence, the proposed scheme can achieve real-time performance and can be used in mobile platform multi-video processing applications.
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