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Design and implementation of a Hybrid High Speed Area Efficient Parallel Prefix Adder in an FPGA
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 58 - Number 1 |
| Year of Publication: 2012 |
| Authors: S. V. Padmajarani, M. Muralidhar |
10.5120/9246-3410
|
S. V. Padmajarani, M. Muralidhar . Design and implementation of a Hybrid High Speed Area Efficient Parallel Prefix Adder in an FPGA. International Journal of Computer Applications. 58, 1 ( November 2012), 17-21. DOI=10.5120/9246-3410
Abstract
Parallel prefix adder is the most flexible and widely used for binary addition. Parallel Prefix adders are best suited for VLSI implementation. A number of parallel prefix adder structures have been proposed over the past years intended to optimize area, fan-out, logic depth and inter connect count. This paper presents a hybrid high speed and area efficient adder architecture, based on parallel prefix computation by using four operators namely black, gray, O3-black and O3-gray operators. These operators are designed using multiplexers. The proposed hybrid architecture is implemented with 16-bit width operands on Xilinx Spartan 3E FPGA. The experimental results indicate that the proposed architecture is much faster and area efficient.
References
- Skalansky "conditional sum additions logic" IRE Transactions, Electronic Computers, vol, EC – 9, pp, 226 - 231, June 1960.
- Kogge P, Stone H, "A parallel algorithm for the efficient solution of a general class Recurrence relations", IEEE Trans. Computers, vol. C-22, No. 8, pp 786-793, Aug. 1973.
- Brent R, Kung H, "A regular layout for parallel adders". IEEE Trans, computers, Vol. C-31, no. 3, pp 260-264, March1982.
- Ladner R, Fischer M,"Parallel prefix computation ", J. ACM, vol. 27, no. 4, pp 831-838, Oct. 1980.
- Han T, Carlson D, "Fast area-efficient VLSI adders", Proc. 8th. symp. Comp. Arit. pp. 49-56, Sep. 1987.
- Jianhua LiuZhu, Haikun, Chung-Kuan Cheng, John Lillis, "Optimum prefix Adders in a Comprehensive Area,Timing and power Design Space". , Proceeding of the 2007 Asia and South pacific Design Automation conference. Washington, pp. 609-615,jan 2007.
- Taeko Matsunaga and Yusuka Matsunaga. , "Timing-Constrained Area minimization Algorithm for parallel prefix adders", IEICE TRANS, Fundamentals, vol. E90-A, No. 12 Dec, 2007.
- Taeko Matsunaga and Shinji Kimura, Yusuka Matsunaga, "Synthesis of parallel prefix adders considering switching activities",IEEE International Conference on computer design, , pp. 404-409, 2008
- Giorgos Dimitrakopoulos and Dimitric Nikolos, "High Speed Parallel –Prefix VLSI Ling Adders", IEEE Trans on computers, Vol. 54, No. 2, Feb 2005
- V. Choi and E. E. Swartz lander, Ir, "Parallel Prefix adder design with matrix representation",, in Proc. 17th IEEE symp, comput. Arithmatic (ARITH), PP 90-98,2005
- John F. Wakerly, Digital Design Principles and Practices, 4th Edition, Pearson Education, 2009.
- S. V. Padmajarani and M. Muralidhar, "A New Approach to implement Parallel Prefix Adders in an FPGA", IJERA,Vol. 2, No. 4, pp. 1524-1528, July-August,2012.
- S. V. Padmajarani and M. Muralidhar, "Comparison of Parallel Prefix Adders Performance in an FPGA", IJERD, Vol. 3, No6, pp. 62-67 , September 2012.
- S. V. Padmajarani and M. Muralidhar, "A Hybrid Parallel Prefix Adder for high speed computing", Proc. 7th National Conference on Advances in Electronics and Communications(ADELCOs, National Engineering College, Kovilpatti, India, 2011.
- P. Ramanathan,P. T. Vanathi,"A Novel Power Dealy Optimized 32-bit Parallel Prefix Adder for High Speed Computing", International Journal of Recent Rrends in Engineering, Vol2, No. 6,pp58-62, November2009.
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