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Implementation of Digital Image Morphological Algorithm on FPGA using Hardware Description Languages
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 57 - Number 5 |
| Year of Publication: 2012 |
| Authors: R. Arunmozhi, G. Mohan |
10.5120/9107-3253
|
R. Arunmozhi, G. Mohan . Implementation of Digital Image Morphological Algorithm on FPGA using Hardware Description Languages. International Journal of Computer Applications. 57, 5 ( November 2012), 1-4. DOI=10.5120/9107-3253
Abstract
In this work, an implementation of linear filtering and morphological image operation using a EDK 11. 1 FPGA Spartan 3E is implemented in Field Programmable Gate Array this technology has become a viable target for the implementation of real time algorithms suited to video image processing and image processing applications. The unique architecture of the FPGA has allowed the technology to be used in many applications encompassing all aspects of video image processing and image processing. Among those algorithms, dilation, erosion and linear filtering, represent a basic set of image operations for a number of applications. the system is connected to a USB port of a personal computer, which in that way form a powerful and low-cost design station. A comparison between different HDL language and the described FPGA-based implementation is presented. Image processing algorithms are conventionally implemented in DSP, ARM processors and some special purpose processors. However all these implementation styles are limited by throughput which becomes very critical parameter for several image processing applications. The FPGA technologies offer basic digital blocks with flexible interconnections to achieve high speed digital hardware realization. The image will be transferred from computer to FPGA board using JTAG cable. After performing the required filtering process the result will be transferred back to computer.
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- www. xilinx. com
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