We apologize for a recent technical issue with our email system, which temporarily affected account activations. Accounts have now been activated. Authors may proceed with paper submissions. PhDFocusTM
CFP last date
20 November 2024
Call for Paper
December Edition
IJCA solicits high quality original research papers for the upcoming December edition of the journal. The last date of research paper submission is 20 November 2024

Submit your paper
Know more
Reseach Article

Energy Efficient Implementation for Arithmetic Application in CMOS Full Adders

by T. Thirumurugan, J. Sathish Kumar
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 57 - Number 2
Year of Publication: 2012
Authors: T. Thirumurugan, J. Sathish Kumar
10.5120/9090-3049

T. Thirumurugan, J. Sathish Kumar . Energy Efficient Implementation for Arithmetic Application in CMOS Full Adders. International Journal of Computer Applications. 57, 2 ( November 2012), 42-48. DOI=10.5120/9090-3049

@article{ 10.5120/9090-3049,
author = { T. Thirumurugan, J. Sathish Kumar },
title = { Energy Efficient Implementation for Arithmetic Application in CMOS Full Adders },
journal = { International Journal of Computer Applications },
issue_date = { November 2012 },
volume = { 57 },
number = { 2 },
month = { November },
year = { 2012 },
issn = { 0975-8887 },
pages = { 42-48 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume57/number2/9090-3049/ },
doi = { 10.5120/9090-3049 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:59:27.234797+05:30
%A T. Thirumurugan
%A J. Sathish Kumar
%T Energy Efficient Implementation for Arithmetic Application in CMOS Full Adders
%J International Journal of Computer Applications
%@ 0975-8887
%V 57
%N 2
%P 42-48
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The overall view of this paper is to attain high speed, low power full adder cells with alternative logic cells that lead to have reduced power delay product. Two high-speed and low-power full adder cells designed with an alternative internal logic structure and pass-transistor logic styles that lead to have a reduced power-delay product (PDP). We carried out a comparison against other full-adders reported as having a low PDP, in terms of speed, power consumption and area. All the full-adders were designed with a 0. 18- m CMOS technology, and were tested using a comprehensive test bench that allowed to measure the current taken from the full adder inputs, besides the current provided from the power supply. Post-layout simulations show that the proposed full adders outperform its counterparts exhibiting an average PDP advantage of 80%, with only 40% of relative area. Adder module is the core of many arithmetic operations such as addition, subtraction, multiplication and division with an alternative internal logic structure based on the multiplexing of the Boolean function. To determine the lowest power supply voltage of full adders can tolerate by its correct functionality. Delay in full adder relates the amount of energy spent during the realization of the determined task. The design of the full adder circuit in Micro wind tool that allow measuring the Delay, Area, Power Consumption and Speed.

References
  1. S. Agarwal. , V. K. Pavankumar. , and R. Yokesh. , "Energy-ef?cient high performance circuits for arithmetic units," in Proceeding of 2nd International Conference on VLSI Design, January. 2008, pp. 371–376.
  2. M. Aguirre. , and M. Linares. , "An alternative logic approach to implement high-speed low-power full adder cells," in Proceeding of SBCCI, Florianopolis, Brazil, September. 2005, pp. 166–171.
  3. K. M. Chu. ,and D. Pulfrey. , "A comparison of CMOS circuit techniques: Differential cascode voltage switch logic versus conventional logic," IEEE Journal of Solid-State Circuits, vol. SC-22, no. 4, pp. 528–532, August . 1987.
  4. C. Chang. , J. Gu. , and M. Zhang,. , "A review of 0. 18m full adder performances for tree structured arithmetic circuits," IEEE Transaction of Very Large Scale Integration (VLSI) Systems , vol. 13, no. 6, pp. 686–695, January. 2005.
  5. S. Goel. , A. Kumar. , and M. Bayoumi. , "Design of robust, energy-ef?cient full adders for deep-submicrometer design using hybrid-CMOS logic style," IEEE Transaction of Very Large Scale Integration. (VLSI) Systems, vol. 14, no. 12, pp. 1309–1320, December. 2006.
  6. D. Patel. , P. G. Parate. , P. S. Patil. , and S. Subbaraman. , "ASIC implementation of 1-bit full adder," in Proceedings of 1st International Conference on Emerging Trends Engineering Technology , July . 2008, pp. 463–467.
  7. D. Radhakrishnan. , "Low-voltage low-power CMOS full adder," IEEE Proceedings of Circuits Devices Systems , vol. 148, no. 1, pp. 19–24, February . 2001.
  8. A. M. Shams. , and M. Bayoumi. , "Performance evaluation of 1-bit CMOS adder cells," in Proceedings of . IEEE ISCAS, Orlando, FL, May 1999, vol. 1, pp. 27–30.
  9. M. Suzuki. , M. Suzuki. , N. Ohkubo. , T. Shinbo. , T. Yamanaka. , A. Shimizu. , K. Sasaki. , and Y. Nakagome. , , "A 1. 5 ns 32-b CMOS ALU in double pass-transistor logic," IEEE Journal of Solid-State Circuits, vol. 28, no. 11, pp. 1145–1150, November . 1993.
  10. M. Zhang. , J. Gu. , and C. H. Chang. , "A novel hybrid pass logic with static CMOS output drive full-adder cell," in Proceedings of IEEE International Symposium of Circuits Systems, May 2003, pp. 317–320.
Index Terms

Computer Science
Information Sciences

Keywords

Arithmetic operations delay high speed low power Double Pass –transistor Logic Complementary Pass-transistor Logic