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Study and Design of Low Power Quasi Adiabatic Cross Coupled Inverter

by Samik Samanta
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 57 - Number 15
Year of Publication: 2012
Authors: Samik Samanta
10.5120/9188-3609

Samik Samanta . Study and Design of Low Power Quasi Adiabatic Cross Coupled Inverter. International Journal of Computer Applications. 57, 15 ( November 2012), 6-10. DOI=10.5120/9188-3609

@article{ 10.5120/9188-3609,
author = { Samik Samanta },
title = { Study and Design of Low Power Quasi Adiabatic Cross Coupled Inverter },
journal = { International Journal of Computer Applications },
issue_date = { November 2012 },
volume = { 57 },
number = { 15 },
month = { November },
year = { 2012 },
issn = { 0975-8887 },
pages = { 6-10 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume57/number15/9188-3609/ },
doi = { 10.5120/9188-3609 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:00:30.355180+05:30
%A Samik Samanta
%T Study and Design of Low Power Quasi Adiabatic Cross Coupled Inverter
%J International Journal of Computer Applications
%@ 0975-8887
%V 57
%N 15
%P 6-10
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Power dissipation has been a highly concerned issue in low power VLSI design. The classical approaches of reducing energy dissipation in conventional CMOS circuits include reducing the supply voltages, node capacitances and switching activities. Adiabatic switching technique based on energy recovery principle is one of the techniques to achieve low power VLSI design. In this paper the power dissipation of various adiabatic circuits is calculated using SPICE simulation tool. From the calculated results it has also been found that positive feedback adiabatic logic (PFAL) inverter exhibits minimum power dissipation among all the cross coupled adiabatic inverters. A new adiabatic family has been proposed by swapping NMOS and PMOS transistor of pull up network and pull down network and it has been shown that the new PFAL inverter has 33% less power dissipation than conventional PFAL inverter.

References
  1. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd ed. New York: Addison - Wesley,1993.
  2. M. Pedram, "Power minimization in IC design: principles and applications," ACM Transactions on Design Automation of Electronic Systems, 1(1): 3-56,January 1996
  3. J. S. Denker, "A review of adiabatic computing," inProc. of the Symposium on Low Power Electronics,1994, pp. 94-97.
  4. Jan Rabey,Massoud Pendram, Low power Design Methodologies:5-7,Kluwer Academic Publishers,5th edition. 2002
  5. PD Khandekar, S Subbaraman ,Manish Patil"Low power Digital Design Using Energy-Recovery Adiabatic Logic" International Journal of Engineering Research and Industrial Apllications,Vol1,No. III,pp199-2081994, pp. 94-97.
  6. S. Samanta "Adiabatic Computing" a contemporary review" 4th international conference on computer and devices for communication : codec 09" Kolkata 2009.
  7. S. Samanta" Power Efficient VLSI Inverter Design using Adiabatic Logic and Estimation of Power dissipation using VLSI-EDA Tool" Special issue of International Journal of computer communication Technology. vol 2. isuue 2,3,4. pp300-303. 2010.
  8. Arsalan, M. ; Shams, M. "An investigation into transistor-based adiabatic logic styles. " Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on 20-23 June 2004 Page(s):1 – 4
Index Terms

Computer Science
Information Sciences

Keywords

VLSI PFAL SPICE adiabatic