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Reconfigurable Design of GSM Digital down Converter for Enhanced Resource Utilization

by Rajesh Mehra, Swapna Devi, S. S. Pattnaik
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 57 - Number 11
Year of Publication: 2012
Authors: Rajesh Mehra, Swapna Devi, S. S. Pattnaik
10.5120/9161-3318

Rajesh Mehra, Swapna Devi, S. S. Pattnaik . Reconfigurable Design of GSM Digital down Converter for Enhanced Resource Utilization. International Journal of Computer Applications. 57, 11 ( November 2012), 41-47. DOI=10.5120/9161-3318

@article{ 10.5120/9161-3318,
author = { Rajesh Mehra, Swapna Devi, S. S. Pattnaik },
title = { Reconfigurable Design of GSM Digital down Converter for Enhanced Resource Utilization },
journal = { International Journal of Computer Applications },
issue_date = { November 2012 },
volume = { 57 },
number = { 11 },
month = { November },
year = { 2012 },
issn = { 0975-8887 },
pages = { 41-47 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume57/number11/9161-3318/ },
doi = { 10.5120/9161-3318 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:00:11.686233+05:30
%A Rajesh Mehra
%A Swapna Devi
%A S. S. Pattnaik
%T Reconfigurable Design of GSM Digital down Converter for Enhanced Resource Utilization
%J International Journal of Computer Applications
%@ 0975-8887
%V 57
%N 11
%P 41-47
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper a hybrid approach is presented to design and implement a GSM digital down convertor for enhanced resource utilization. The proposed DDC has been implemented by hybridizing the multiplier less and multiplier based decimators. A multiplier less CIC decimator has been used to reduce the cost by reducing the multiplier requirement. Two computationally efficient equiripple polyphase decomposition structure based decimators have been to reduce the filter order and hardware complexity. The embedded multipliers, LUTs and BRAMs have been efficiently utilized to enhance the system performance and resource utilization. The proposed GSM DDC has been designed and simulated Matlab and Simulink, synthesized with Xilinx Synthesis Tool and implemented on Virtex-II Pro based xc2vp20 FPGA device. The proposed design has shown a minimum period of 159. 96 MHz with enhance resource utilization ranging from 4-12 % in terms slices, flip flops LUTs, BRAMs and multipliers.

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Index Terms

Computer Science
Information Sciences

Keywords

BRAM DDC FPGA LUT GSM

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