We apologize for a recent technical issue with our email system, which temporarily affected account activations. Accounts have now been activated. Authors may proceed with paper submissions. PhDFocusTM
CFP last date
20 November 2024
Call for Paper
December Edition
IJCA solicits high quality original research papers for the upcoming December edition of the journal. The last date of research paper submission is 20 November 2024

Submit your paper
Know more
The week's pick
Responsive image
An Efficient Restoration Method for the Faint Dot Matrix Images

Ao Zhu Peng Cao
Random Articles
Reseach Article

Reconfigurable Design of GSM Digital down Converter for Enhanced Resource Utilization

by Rajesh Mehra, Swapna Devi, S. S. Pattnaik
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 57 - Number 11
Year of Publication: 2012
Authors: Rajesh Mehra, Swapna Devi, S. S. Pattnaik
10.5120/9161-3318

Rajesh Mehra, Swapna Devi, S. S. Pattnaik . Reconfigurable Design of GSM Digital down Converter for Enhanced Resource Utilization. International Journal of Computer Applications. 57, 11 ( November 2012), 41-47. DOI=10.5120/9161-3318

@article{ 10.5120/9161-3318,
author = { Rajesh Mehra, Swapna Devi, S. S. Pattnaik },
title = { Reconfigurable Design of GSM Digital down Converter for Enhanced Resource Utilization },
journal = { International Journal of Computer Applications },
issue_date = { November 2012 },
volume = { 57 },
number = { 11 },
month = { November },
year = { 2012 },
issn = { 0975-8887 },
pages = { 41-47 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume57/number11/9161-3318/ },
doi = { 10.5120/9161-3318 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:00:11.686233+05:30
%A Rajesh Mehra
%A Swapna Devi
%A S. S. Pattnaik
%T Reconfigurable Design of GSM Digital down Converter for Enhanced Resource Utilization
%J International Journal of Computer Applications
%@ 0975-8887
%V 57
%N 11
%P 41-47
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper a hybrid approach is presented to design and implement a GSM digital down convertor for enhanced resource utilization. The proposed DDC has been implemented by hybridizing the multiplier less and multiplier based decimators. A multiplier less CIC decimator has been used to reduce the cost by reducing the multiplier requirement. Two computationally efficient equiripple polyphase decomposition structure based decimators have been to reduce the filter order and hardware complexity. The embedded multipliers, LUTs and BRAMs have been efficiently utilized to enhance the system performance and resource utilization. The proposed GSM DDC has been designed and simulated Matlab and Simulink, synthesized with Xilinx Synthesis Tool and implemented on Virtex-II Pro based xc2vp20 FPGA device. The proposed design has shown a minimum period of 159. 96 MHz with enhance resource utilization ranging from 4-12 % in terms slices, flip flops LUTs, BRAMs and multipliers.

References
  1. B. B. Carvalho, A. J. N. Batista, F. Patrício, M. Correia, H. Fernandes, J. Sousa, and C. A. F. Varandas, "Multi-Rate DSP/FPGA-Based Real-Time Acquisition and Control on the ISTTOK Tokamak" IEEE Transactions on Nuclear Science, VOL. 55, NO. 1, pp. 54-58, February 2008.
  2. K. N. Macpherson and R. W. Stewart "Area efficient FIR filters for high speed FPGA Implementation", IEE Proceedings on Vision Image and Signal Processing, Vol. 153, No. 6, pp711-720, December 2006.
  3. Amir Beygi, Ali Mohammadi, Adib Abrishamifar. "An FPGA-Based Irrational Decimator for Digital Receivers" IEEE International Symposium on Signal Processing and its Applications (ISSPA), pp. 1-4, 2007.
  4. Veerendra Bhargav Alluri, J. Robert Heath, Michael Lhamon "A New Multichannel, Coherent Amplitude Modulated, Time-Division Multiplexed, Software-Defined Radio Receiver Architecture, and Field Programmable Gate Array Technology Implementation" IEEE Transactions on Signal Processing, Vol. 58, No. 10, pp. 5369-5384, October 2010.
  5. Irene Herranz, Stefan Fikar, Erwin Biebl, Arpad L. Scholtz, "Automotive Multi-standard RF Front-end for GSM, WCDMA and Mobile WiMAX" IEEE Wireless Telecommunications Symposium (WTS), pp. 1-5, 2009.
  6. Ali Montazeri, Kamran Kiasaleh "Design and Performance Analysis of a Low Complexity Digital Clock Recovery Algorithm for Software-Defined Radio Applications" IEEE Transactions on Consumer Electronics, Vol. 56, No. 3, pp. 1258-1263, August 2010.
  7. Pedro Cruz, Nuno Borges Carvalho, Kate A. Remley "Designing and Testing Software Defined Radios" IEEE Microwave magazine, pp. 83-94, June 2010.
  8. Takashi Shono, Yushi Shirato, Hiroyuki Shiba, Kazuhiro Uehara, Katsuhiko Araki, Masahiro Umehira, "IEEE 802. 11 Wireless LAN Implemented on Software Defined Radio With Hybrid Programmable Architecture" IEEE Transactions on Wireless Communications, Vol. 4, No. 5, pp. 2299-2308, September 2005.
  9. Benny Bing, Nikil Jayant, "A Cell Phone for all standards" IEEE Spectrum on Communications, pp. 34-39, May 2002.
  10. Petri Isomäki, Nastooh Avessta, "An Overview of Software Defined Radio Technologies" TUSC Technical Report No. 654, pp. 1-16, December-2004.
  11. Texas Instruments GC4116 Multi-Standard QUAD DUC Chip Data Sheet, SLWS135A, pp. 1-18, June 2002.
  12. Texas Instruments GC4016 Multi-Standard QUAD DDC Chip Data Sheet, SLWS133A, pp. 1-26, August 2001.
  13. Navid Lashkarian, Ed Hemphill, Helen Tarn, Hemang Parekh, and Chris Dick "Reconfigurable Digital Front-End Hardware for Wireless Base-Station Transmitters: Analysis, Design and FPGA Implementation" IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 54, No. 8, pp. 1666-1677, August 2007
  14. Xiaoxiao Xu, Xianzhong Xie, Fei Wang, "Digital Up and Down Converter in IEEE 802. 16d" IEEE International Conference on Signal Processing (ICSP), Vol. 1, pp. 17-20, 2006.
  15. Saad Mahboob, "FPGA Implementation of Digital Up/Down Convertor for WCDMA System" IEEE International Conference on Advanced Communication Technologies (ICACT), pp. 757-760, 2010.
  16. Feiteng Luo, Weidong Chen, "An Economical TDM Design of Multichannel Digital Down Converter" IEEE International Conference on Signal Processing (ICSP), pp. 498-501, 2008.
  17. F. J. A. de Aquino, C. A. F. da Rocha, and L. S. Resende, "Design of CIC filters for software radio system," IEEE International Conference on Acoustics, Speech, Signal Processing (ICASSP), pp. III-225-228, 2006.
  18. D. Babic, J. Vesma, and M. Renfors, "Decimation by irrational factor using CIC filter and linear interpolation," IEEE International Conference on Acoustics, Speech, Signal Processing (ICASSP), pp. 3677-3680, 2001.
  19. Yan Wang, Hui-mei Yuan, Wen Chen, "Design of CIC Filter and DFC used in Energy Metering IC" IEEE International Conference on Industrial Electronics and Applications (ICIEA) , pp. 1270-1274, 2009.
  20. G. J. Dolecek, and J. D. Carmona, "A new cascaded modified CIC-cosine decimation filter," IEEE International Symposium on Circuits and Systems (ISCAS), Vol-4, pp. 3733-3736, 2005.
  21. W. A. Abu-Al-Saud, and G. L. Stuber, "Modified CIC filter for sample rate conversion in software radio systems," IEEE Signal Processing Letters, Vol. 10, Issue: 5, pp. 152-154, May 2003.
  22. Majid Salal Naghmash, Mohd Fadzil Ain "Design of minimum error digital down-converter (DDC) for GSM mask requirements" Journal of Engineering and Technology Research Vol. 1 (5), pp. 91-101, August 2009.
  23. Rajesh Mehra, Dr. Swapna Devi' "Efficient Hardware Co-Simulation of down Convertor for Wireless Communication Systems" International Journal of VLSI Design & Communication Systems (VLSICS), pp. 13-21, Vol. 1, No. 2, June 2010.
Index Terms

Computer Science
Information Sciences

Keywords

BRAM DDC FPGA LUT GSM

Powered by PhDFocusTM