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Reseach Article

VLSI Architecture of Pipelined Booth Wallace MAC Unit

by Naveen Kumar, Manu Bansal, Navnish Kumar
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 57 - Number 11
Year of Publication: 2012
Authors: Naveen Kumar, Manu Bansal, Navnish Kumar
10.5120/9157-2669

Naveen Kumar, Manu Bansal, Navnish Kumar . VLSI Architecture of Pipelined Booth Wallace MAC Unit. International Journal of Computer Applications. 57, 11 ( November 2012), 14-18. DOI=10.5120/9157-2669

@article{ 10.5120/9157-2669,
author = { Naveen Kumar, Manu Bansal, Navnish Kumar },
title = { VLSI Architecture of Pipelined Booth Wallace MAC Unit },
journal = { International Journal of Computer Applications },
issue_date = { November 2012 },
volume = { 57 },
number = { 11 },
month = { November },
year = { 2012 },
issn = { 0975-8887 },
pages = { 14-18 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume57/number11/9157-2669/ },
doi = { 10.5120/9157-2669 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:00:08.897482+05:30
%A Naveen Kumar
%A Manu Bansal
%A Navnish Kumar
%T VLSI Architecture of Pipelined Booth Wallace MAC Unit
%J International Journal of Computer Applications
%@ 0975-8887
%V 57
%N 11
%P 14-18
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper describes the pipelined architecture of high-speed modified Booth Wallace Multiply and Accumulator. The proposed multiply and accumulate circuits are based on the Booth algorithm and the pipelining techniques, which are most widely used to accelerate the multiplication speed. A 32-bit MAC Unit is designed in which the multiplication is done using the Modified Booth Wallace Multiplier and in the final stage addition of multiplier and in accumulator the Carry Select Adder is used and the pipelining is done in the Booth Multiplier and Wallace Tree. This MAC is described in VHDL and synthesized the circuit using 90 nm standard cell library on FPGA and Synopsys Design Compiler. This MAC has higher speed than conventional Booth Wallace MAC Unit.

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Index Terms

Computer Science
Information Sciences

Keywords

Multiplier Adder Pipelining High-speed modified Booth algorithm Synopsys Design Compiler FPGA