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Area Efficient FPGA Implementation of Sobel Edge Detector for Image Processing Applications
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 56 - Number 16 |
| Year of Publication: 2012 |
| Authors: Rajesh Mehra, Rupinder Verma |
10.5120/8973-3086
|
Rajesh Mehra, Rupinder Verma . Area Efficient FPGA Implementation of Sobel Edge Detector for Image Processing Applications. International Journal of Computer Applications. 56, 16 ( October 2012), 7-11. DOI=10.5120/8973-3086
Abstract
In this Paper an efficient method of FPGA based design and implementation of area efficient Sobel Edge detection filter is presented using a combination of hardware and software components. The FPGA provides the necessary hardware for image processing algorithms with flexibility to support Sobel edge detection algorithm. A pipelined method is used to implement the edge detection filter. This approach is useful to improve the system performance by taking advantage of available look up tables, routing resources and shift registers available on target device. The proposed 2-D filter is designed using matlab, synthesized with Xilinx ISE 10. 1 and implemented on Virtex II Pro based xc2vp30-7-FF896 FPGA device. Results show better performance of proposed design in terms of area utilization.
References
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