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Design and Analysis of a Linear Feedback Shift Register with Reduced Leakage Power
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 56 - Number 14 |
| Year of Publication: 2012 |
| Authors: M. Janaki Rani, S. Malarkkan |
10.5120/8957-3159
|
M. Janaki Rani, S. Malarkkan . Design and Analysis of a Linear Feedback Shift Register with Reduced Leakage Power. International Journal of Computer Applications. 56, 14 ( October 2012), 9-13. DOI=10.5120/8957-3159
Abstract
As the CMOS technology is scaling down, leakage power has become one of the most critical design concerns for the chip designer. This paper proposes a low leakage linear feedback shift register that can be used in a crypto-processor. In this work, three bit, four bit and five bit linear feedback shift registers are implemented in 90nm and 65nm technology . This paper also proposes two leakage reduction techniques such as reverse body bias and transistor stack, which are applied to the above circuits. The leakage power of the circuits is analyzed with and without the application of reduction techniques. The results show that for all the circuits the combined effect of (RBB + Stack ) leakage reduction method gives the least leakage power of 23. 16nW, 47. 53nWand 72. 18nW for 3-bit, 4-bit and 5-bit linear feedback shift register respectively at 90nm technology. In 65nm technology the combined leakage reduction method gives the least leakage power of 33. 86nW, 64. 73nWand 95. 14nW respectively. The circuits have been simulated with HSPICE using MOSFET models of level 54 with a supply voltage of 1 volt.
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