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Leakage Power Reduction in CMOS VLSI Circuits
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 55 - Number 8 |
| Year of Publication: 2012 |
| Authors: Pushpa Saini, Rajesh Mehra |
10.5120/8778-2721
|
Pushpa Saini, Rajesh Mehra . Leakage Power Reduction in CMOS VLSI Circuits. International Journal of Computer Applications. 55, 8 ( October 2012), 42-48. DOI=10.5120/8778-2721
Abstract
Leakage power has become a serious concern in nanometer CMOS technologies. In the past, the dynamic power has dominated the total power dissipation of CMOS devices. However, with the continuous trend of technology scaling, leakage power is becoming a main contributor to power consumption. In the past many methods had been proposed for leakage power reduction like forced stack, sleepy stack, sleepy keeper, dual sleep approach etc. using techniques like transistor sizing, multi-Vth, dual-Vth, stacking transistors etc. In this paper, new methods have been proposed for the leakage power reduction in 90nm technology. The proposed methods will be compared with the previous existing leakage reduction techniques. The result is simulated using Microwind 3. 1 in 90nm CMOS technology at room temperature.
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