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Efficient Hardware Implementation of SHA-3 Candidate Grostl using FPGA

by Syed Muhammad Adnan, Arshad Aziz
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 55 - Number 15
Year of Publication: 2012
Authors: Syed Muhammad Adnan, Arshad Aziz
10.5120/8829-2963

Syed Muhammad Adnan, Arshad Aziz . Efficient Hardware Implementation of SHA-3 Candidate Grostl using FPGA. International Journal of Computer Applications. 55, 15 ( October 2012), 6-11. DOI=10.5120/8829-2963

@article{ 10.5120/8829-2963,
author = { Syed Muhammad Adnan, Arshad Aziz },
title = { Efficient Hardware Implementation of SHA-3 Candidate Grostl using FPGA },
journal = { International Journal of Computer Applications },
issue_date = { October 2012 },
volume = { 55 },
number = { 15 },
month = { October },
year = { 2012 },
issn = { 0975-8887 },
pages = { 6-11 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume55/number15/8829-2963/ },
doi = { 10.5120/8829-2963 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:57:19.098178+05:30
%A Syed Muhammad Adnan
%A Arshad Aziz
%T Efficient Hardware Implementation of SHA-3 Candidate Grostl using FPGA
%J International Journal of Computer Applications
%@ 0975-8887
%V 55
%N 15
%P 6-11
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In 2007 NIST announced a public competition to develop a new cryptographic hash algorithm. This competition was announced due to the fact that in recent years, several successful attacks have been reported against SHA-1, thus raised significant alarming conditions against SHA-2. This new algorithm will replace the SHA-2 and can be used in various security applications in the information infrastructure. This paper focuses on efficient implementation of one of the SHA-3 candidates and round-3 finalist Grøstl on FPGA. The aim of this work is to achieve high throughput to area ratio (TPA) simultaneously by achieving high throughput by considering tradeoff between area and speed. The design is implemented as fully autonomous with both permutations P and Q are executed in parallel, and are equipped with I/O wrapper. The developed hardware has two designs, first with S-box is implemented using Look-Up-Table (LUT) or Distributed Memory and second with S-box implemented as Block RAM (BRAM). The implementation results obtained using virtex-5, when S-box is implemented as LUT has a throughput of 9. 360Gbps and occupied 2253 Slices including I/O wrapper, thus achieves TPA of 4. 154 and when S-box implemented as BRAM has throughput of 5. 565Gbps and occupied 1356 Slices with wrapper, thus achieves 4. 104 throughput per unit area (TPA) .

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Index Terms

Computer Science
Information Sciences

Keywords

Efficient Hardware

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