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Efficient Hardware Implementation of SHA-3 Candidate Grostl using FPGA

by Syed Muhammad Adnan, Arshad Aziz
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 55 - Number 15
Year of Publication: 2012
Authors: Syed Muhammad Adnan, Arshad Aziz
10.5120/8829-2963

Syed Muhammad Adnan, Arshad Aziz . Efficient Hardware Implementation of SHA-3 Candidate Grostl using FPGA. International Journal of Computer Applications. 55, 15 ( October 2012), 6-11. DOI=10.5120/8829-2963

@article{ 10.5120/8829-2963,
author = { Syed Muhammad Adnan, Arshad Aziz },
title = { Efficient Hardware Implementation of SHA-3 Candidate Grostl using FPGA },
journal = { International Journal of Computer Applications },
issue_date = { October 2012 },
volume = { 55 },
number = { 15 },
month = { October },
year = { 2012 },
issn = { 0975-8887 },
pages = { 6-11 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume55/number15/8829-2963/ },
doi = { 10.5120/8829-2963 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:57:19.098178+05:30
%A Syed Muhammad Adnan
%A Arshad Aziz
%T Efficient Hardware Implementation of SHA-3 Candidate Grostl using FPGA
%J International Journal of Computer Applications
%@ 0975-8887
%V 55
%N 15
%P 6-11
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In 2007 NIST announced a public competition to develop a new cryptographic hash algorithm. This competition was announced due to the fact that in recent years, several successful attacks have been reported against SHA-1, thus raised significant alarming conditions against SHA-2. This new algorithm will replace the SHA-2 and can be used in various security applications in the information infrastructure. This paper focuses on efficient implementation of one of the SHA-3 candidates and round-3 finalist Grøstl on FPGA. The aim of this work is to achieve high throughput to area ratio (TPA) simultaneously by achieving high throughput by considering tradeoff between area and speed. The design is implemented as fully autonomous with both permutations P and Q are executed in parallel, and are equipped with I/O wrapper. The developed hardware has two designs, first with S-box is implemented using Look-Up-Table (LUT) or Distributed Memory and second with S-box implemented as Block RAM (BRAM). The implementation results obtained using virtex-5, when S-box is implemented as LUT has a throughput of 9. 360Gbps and occupied 2253 Slices including I/O wrapper, thus achieves TPA of 4. 154 and when S-box implemented as BRAM has throughput of 5. 565Gbps and occupied 1356 Slices with wrapper, thus achieves 4. 104 throughput per unit area (TPA) .

References
  1. "Cryptographic Hash-Function Basics: Definitions, Implications, and Separations for Preimage Resistance, Second-Preimage Resistance, and Collision Resistance", Department. Of Computer Science, University of California, Davis, California, 95616, USA, Appears in 11th International Workshop, Fast Software Encryption (FSE 2004), Delhi, India, February 5-7, 2004, LNCS 3017, pp. 371-388, 2004. www. cs. ucdavis. edu/~rogaway/papers/relates. pdf
  2. National Institute of Standards and Technology (NIST), "Cryptographic Hash Algorithm Competition, Federal Register, Vol. 72, No. 212, Friday, November 2, 2007, Notices http://csrc. nist. gov/groups/ST/hash/sha-3/index. html
  3. National Institute of Standards and Technology. Cryptographic Hash Project, 2007. Federal Register, Vol. 72, No. 212, Friday, November 2, 2007, Notices. Available online at http://www. nist. gov/hash-competition.
  4. SHA-3 Hardware Implementations: http://ehash. iaik. tugraz. at/wiki/SHA-3_Hardware-Implementations
  5. SHA-3 Hardware Implementation, Cryptographic Engineering Research Group, George Mason University, Washington, http://cryptography. gmu. edu/research/index. php
  6. SHA-3 HARDWARE IMPLEMENTATION, Research Center for Information Security http://www. rcis. aist. go. jp/project/index-en. html
  7. Performance Evaluation of SHA-3 Candidates in ASIC and FPGA, Center for Embedded Systems for Critical Applications (CESCA), ECE, Virginia Tech, available at http://rijndael. ece. vt. edu/sha3/relatedwork. html
  8. Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski, Rabia Shahid, and Malik Umar Sharif. "Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs". IACR Cryptology ePrint Archive, Vol. 2012 (2012), p. 368. The third SHA-3 candidate conference, Washington, DC, 22-23 March 2012, pp. 57-75.
  9. E. Homsirikamol, M. Rogawski, and K. Gaj, "Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs," LNCS 6917, Cryptographic Hardware and Embedded Systems workshop, CHES 2011, Nara, Japan, Sep. 28-Oct. 1, Lecture Notes in Computer Science, Volume 6917, pp. 491-506 ,2011.
  10. E. Homsirikamol, M. Rogawski, and K. Gaj, "Comparing Hardware Performance of Round 3 SHA-3 Candidates using Multiple Hardware Architectures in Xilinx and Altera FPGAs", ECRYPT II hash workshop 2011,Tallinn, Estonia, May 19-20, 2011, pp. 1-15.
  11. B. Baldwin, N. Hanley, M. Hamilton, L. Lu, A. Byrne, M. O'Neill and W. P. Marnane, "FPGA Implementations of the Round Two SHA-3 Candidates," The Second SHA-3 Candidate Conference, Santa Barbara, pp. 1-18(2010), Aug. 23-24, 2010.
  12. S. Matsuo, M. Knezevic, P. Schaumont, I. Verbauwhede, A. Satoh, K. Sakiyama, and K. Ota, "How Can We Conduct Fair and Consistent Hardware Evaluation for SHA-3 Candidate?" The Second SHA-3 Candidate Conference, 2010, Santa Barbara, pp. 1-15(2010), Aug. 23-24, 2010.
  13. Kazuyuki Kobayashi, Jun IkegamiS. Matsuo, K. Sakiyama, and K. Ohta, "Evaluation of Hardware Performance for the SHA-3 Candidates Using SASEBO-GII," The Second SHA-3 Candidate Conference, 2010, Aug. 23-24, 2010, pp. 18-25.
  14. Brian Baldwin, Andrew Byrne, Mark Hamilton, Neil Hanley, Robert P. McEvoy, Weibo Pan and William P. Marnane "FPGA Implementations of SHA-3 Candidates: CubeHash, Grøstl, LANE, Shabal and Spectral Hash", Department of Electrical & Electronic Engineering, Claude Shannon Institute for Discrete Mathematics, Coding and Cryptography, University College Cork, Cork, IRELAND, 12th Euro micro Conference on Digital System Design, Architectures, Methods and Tools, 2009, 27-29 Aug. 2009 , pp. 783 – 79
  15. Jungk, B. , Reith, "On FPGA-based implementations of Grøstl". International Conference on Reconfigureurable Computing and FPGAs, 2010, pp. 316-321.
  16. P. Gauravaram, L. R. Knudsen, K. Matusiewicz, F. Mendel, C. Rechberger, M. Schl¨affer, and S. S. Thomsen. Grøstl- a SHA-3 candidate Submission to NIST (Round 3), University of California Santa Barbara, Santa Barbara, 2011. Available: http: http //www. groestl. info (2011/11/25).
  17. D. Canright. A Very Compact S-Box for AES. In J. R. Rao and B. Sunar, editors, CHES, volume 3659 of LNCS, pages 441-455, Springer, 2005
  18. Edwin NC Mui. Practical Implementation of Rijndael S-Box Using Combinational Logic. Available at http://www. xess. com/projects/Rijndael_SBox. pdf
  19. Vincent Rijmen, "Efficient implementation of the Rijndael S-box", Katholieke University Leuven, Dept. ESAT. Belgium.
Index Terms

Computer Science
Information Sciences

Keywords

Efficient Hardware

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