The week's pick
Random Articles
Reseach Article
Detection and Diagnosis of Faults in the Routing Resources of a SRAM based FPGAs
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 53 - Number 13 |
| Year of Publication: 2012 |
| Authors: Jamuna. S, V. K. Agrawal |
10.5120/8481-2421
|
Jamuna. S, V. K. Agrawal . Detection and Diagnosis of Faults in the Routing Resources of a SRAM based FPGAs. International Journal of Computer Applications. 53, 13 ( September 2012), 18-22. DOI=10.5120/8481-2421
Abstract
Field programmable gate arrays (FPGAs) are the reconfigurable logic devices which are widely used in many applications like system prototyping, complex computing systems, automotive electronics and mobile devices. FPGAs have become very popular at present because of their features like high logic capacity, reconfigurability and regular structure with less area cost. However, increase in density and complexity also has resulted in more probability of defects. FPGAs are prone to different types of faults similar to other complicated integrated circuit chips. Faults may occur due to many reasons like environmental conditions or aging of the device. The rate of occurrence of permanent faults can be quite high in emerging technologies, and hence there is a need for periodic testing of such FPGAs. To effectively deal with the increased defect density, we need efficient methods for fault detection and correction. Here, we present an approach for testing FPGA interconnect that exploits the reprogramability of an FPGA to create built-in self test (BIST) logic by configuring it only during off-line testing. In this way, testability is achieved without any area overhead, since the BIST logic "disappears" when the circuit is reconfigured for its normal system operation. We have used XILINX ISE12. 1 for simulation and synthesis.
References
- Xiaoling Sun, "A Unified Global and Local Interconnect Test Scheme for Xilinx XC4000 FPGAs" in IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 53, NO. 2, APRIL 2004
- Dereck. A. Fernandes, Ian. G. Harris "Application of BIST for interconnect testing of FPGAs" in International test conference 2003.
- C. Stroud, S. Konala, P. Chen, and M. Abramovici, "Built-in self-test of logic blocks in FPGAs," Proc. IEEE VLSI Test Symp. , pp. 387-392,1996
- B. Dutton and C. Stroud, "Built-In Self-Test of Configurable Logic Blocks in Virtex-5 FPGAs," Proc. IEEE Southeastern Symp. on System Theory, pp. 230-234, 2009.
- Ian Kuon, Russel Tessier and Jonathan Rose, " FPGA architecture : Survey and challenges" text book.
- X. Sun, J. Xu, B. Chan, and P. Trouborst, "Novel technique for built-in self-test of FPGA interconnects," in Proc. IEEE Int. Test Conf. , 2000,pp. 795–803.
- F. Lombardi, D. Ashen, X. Chen, and W. K. Huang, "Diagnosing programmable interconnect systems for FPGAs," in Proc. ACM/SIGDA Int. Symp. FPGAs, 1996, pp. 100–106.
- H. Michinishi, T. Yokohira, and T. Okamoto, "A test methodology for interconnect structures of LUT-based FPGAs," in Proc. IEEE Asian Test Symp. , 1996, pp. 68–74.
- M. Renovell, J. M. Portal, J. Figueras, and Y. Zorian, "Testing the interconnect of RAM-based FPGAs," IEEE Design Test Comput. , pp. 45–50,1998.
- C. Stroud, S. Wijesuriya, C. Hamilton, and M. Abramovici, "Built-in self-test of FPGA interconnect," in Proc. IEEE Int. Test Conf. , 1998, pp. 404–410.
- M. Renovell, J. M. Portal, J. Figueras, and Y. Zorian, "Testing the local interconnect resources of SRAM-based FPGAs," J. Electronic Testing:Theory Applicat. , pp. 513–520, 2000.
- T. Liu, F. Lombardi, and J. Salinas, "Diagnosis of interconnects and FPICs using a structured walking-1 approach," in Proc. IEEE VLSI Test Symp. , 1995, pp. 256–261.
- W. K. Huang, X. T. Cheng, and F. Lombardi, "On the diagnosis of programmable interconnect systems: Theory and application," in Proc. IEEE VLSI Test Symp. , Princeton, NJ, 1996, pp. 204–209.
- J. Zhao, F. J. Meyer, and F. Lombardi, "Adaptive fault detection and diagnosis ofRAMinterconnects," J. Electron. Testing: Theory Applicat. , pp. 157–171, 1999.
- A. Hassan, J. Rajski, and V. K. Agrawal, "Testing and diagnosis of interconnects using boundary scan," in Proc. IEEE Int. Test Conf. , 1985, pp. 126–137.
- M. Renovell, J. Figueras, and Y. Zorian, "Test of RAM-based FPGA: Methodology and application to the interconnect," in IEEE VLSI Test Symp. , 1997.
- M. Renovell, J. M. Portal, J. Figueras, and Y. Zorian, "Testing the configurable interconnect/logic interface of SRAM-based FPGAs," in Proc. Design, Automation and Test in Europe Conf. Exhibition, 1999.
- Atul maheshwari, Israel koren and Wayne Burleson, " Techniques for transient fault sensitivity analysis and reduction in VLSI circuits".
- N. R. Shnidman, W. H. Mangione-Smith, and M. Potkonjak, "On-line fault detection for bus-based field programmable gate arrays," IEEE Trans. VLSI Syst. , vol. 6, pp. 656–666, Dec. 1998 . 20] M. Renovell, J. M. Portal, J. Figueras, and Y. Zorian, "Testing the interconnect of RAM-based FPGAs," IEEE Des. Test Comput. , vol. 15, no. 1, pp. 45–50, Jan. –Mar. 1998.
- W. K. Huangin F. J. Meyer, N. Park, F. Lombardi "Testing Memory Modules in SRAM-based Configurable FPGAs" in Proc. IEEE Int. Workshop Memory Technol. , Des. Testing, Aug. 1997, pp. 79–86.
Index Terms
Keywords