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Design and Optimization of Reversible Multiplier Circuit

by Rangaraju H.g, Aakash Babu Suresh, Muralidhara K.n
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 52 - Number 10
Year of Publication: 2012
Authors: Rangaraju H.g, Aakash Babu Suresh, Muralidhara K.n
10.5120/8242-1523

Rangaraju H.g, Aakash Babu Suresh, Muralidhara K.n . Design and Optimization of Reversible Multiplier Circuit. International Journal of Computer Applications. 52, 10 ( August 2012), 44-50. DOI=10.5120/8242-1523

@article{ 10.5120/8242-1523,
author = { Rangaraju H.g, Aakash Babu Suresh, Muralidhara K.n },
title = { Design and Optimization of Reversible Multiplier Circuit },
journal = { International Journal of Computer Applications },
issue_date = { August 2012 },
volume = { 52 },
number = { 10 },
month = { August },
year = { 2012 },
issn = { 0975-8887 },
pages = { 44-50 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume52/number10/8242-1523/ },
doi = { 10.5120/8242-1523 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:52:22.418435+05:30
%A Rangaraju H.g
%A Aakash Babu Suresh
%A Muralidhara K.n
%T Design and Optimization of Reversible Multiplier Circuit
%J International Journal of Computer Applications
%@ 0975-8887
%V 52
%N 10
%P 44-50
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The development of conventional computing technologies faces many challenges for the last couple of decades. Power dissipation in today's computer chips becomes dominant. Reversible computing is a promising alternative to these technologies, with applications in ultra-low power, nano computing, quantum computing, low power CMOS design, optical information processing, bioinformatics etc. In reversible logic the power dissipation can be minimized or even eliminated. In this paper, the 4x4 reversible multiplier circuit is proposed with the design of new reversible gate called RAM gate. The proposed multiplier circuit is efficient compared to the existing designs in terms of gate counts, garbage outputs, constant inputs and quantum cost. The design can be generalized to construct nxn reversible multiplier circuit.

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Index Terms

Computer Science
Information Sciences

Keywords

Reversible logic Constant/Garbage input Garbage output Quantum cost Reversible multiplier

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