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FPGA Implementation of Single Bit Error Correction using CRC

by Pramod S P, Rajagopal A, Akshay S Kotain
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 52 - Number 10
Year of Publication: 2012
Authors: Pramod S P, Rajagopal A, Akshay S Kotain
10.5120/8238-1471

Pramod S P, Rajagopal A, Akshay S Kotain . FPGA Implementation of Single Bit Error Correction using CRC. International Journal of Computer Applications. 52, 10 ( August 2012), 15-19. DOI=10.5120/8238-1471

@article{ 10.5120/8238-1471,
author = { Pramod S P, Rajagopal A, Akshay S Kotain },
title = { FPGA Implementation of Single Bit Error Correction using CRC },
journal = { International Journal of Computer Applications },
issue_date = { August 2012 },
volume = { 52 },
number = { 10 },
month = { August },
year = { 2012 },
issn = { 0975-8887 },
pages = { 15-19 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume52/number10/8238-1471/ },
doi = { 10.5120/8238-1471 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:51:54.765867+05:30
%A Pramod S P
%A Rajagopal A
%A Akshay S Kotain
%T FPGA Implementation of Single Bit Error Correction using CRC
%J International Journal of Computer Applications
%@ 0975-8887
%V 52
%N 10
%P 15-19
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Transferring data between two points is very essential, also the accuracy of the transferred data is vital for some critical applications, but an error during the transmission of data is very common. The Cyclic Redundancy Check (CRC) method is generally used for error detection and correction. In this paper, we have proposed a new technique for error detection and correction in case of CRC-16, which is hardware optimized and works at relatively higher frequency and speed. In the proposed method, it is possible to detect the exact place of single bit error and correct them using minimum hardware. This method involves no look tables and hence is memory efficient. This paper focuses on effective implementation of this method on FPGA.

References
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Index Terms

Computer Science
Information Sciences

Keywords

CRC Field Programmable Gate Array Single bit error correction Parallelism non-lookup technique

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