We apologize for a recent technical issue with our email system, which temporarily affected account activations. Accounts have now been activated. Authors may proceed with paper submissions. PhDFocusTM
CFP last date
20 December 2024
Call for Paper
January Edition
IJCA solicits high quality original research papers for the upcoming January edition of the journal. The last date of research paper submission is 20 December 2024

Submit your paper
Know more
The week's pick
Responsive image
Improved Shuffled Frog Leaping Algorithm with Self-Adaptive Shuffling for Fuzzy Logic PD+G Controller Optimization in Robotic Manipulators

Duc Hoang Nguyen
Random Articles
Reseach Article

FPGA Implementation of Single Bit Error Correction using CRC

by Pramod S P, Rajagopal A, Akshay S Kotain
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 52 - Number 10
Year of Publication: 2012
Authors: Pramod S P, Rajagopal A, Akshay S Kotain
10.5120/8238-1471

Pramod S P, Rajagopal A, Akshay S Kotain . FPGA Implementation of Single Bit Error Correction using CRC. International Journal of Computer Applications. 52, 10 ( August 2012), 15-19. DOI=10.5120/8238-1471

@article{ 10.5120/8238-1471,
author = { Pramod S P, Rajagopal A, Akshay S Kotain },
title = { FPGA Implementation of Single Bit Error Correction using CRC },
journal = { International Journal of Computer Applications },
issue_date = { August 2012 },
volume = { 52 },
number = { 10 },
month = { August },
year = { 2012 },
issn = { 0975-8887 },
pages = { 15-19 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume52/number10/8238-1471/ },
doi = { 10.5120/8238-1471 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:51:54.765867+05:30
%A Pramod S P
%A Rajagopal A
%A Akshay S Kotain
%T FPGA Implementation of Single Bit Error Correction using CRC
%J International Journal of Computer Applications
%@ 0975-8887
%V 52
%N 10
%P 15-19
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Transferring data between two points is very essential, also the accuracy of the transferred data is vital for some critical applications, but an error during the transmission of data is very common. The Cyclic Redundancy Check (CRC) method is generally used for error detection and correction. In this paper, we have proposed a new technique for error detection and correction in case of CRC-16, which is hardware optimized and works at relatively higher frequency and speed. In the proposed method, it is possible to detect the exact place of single bit error and correct them using minimum hardware. This method involves no look tables and hence is memory efficient. This paper focuses on effective implementation of this method on FPGA.

References
  1. Shukla S, Bergmann N W. "Single bit error correction implementation in CRC-16 on FPGA" In: IEEE International Conference on Field-programmable Technology. Brisbane,Australia, 2004: 319-322.
  2. PAN Yun, GE Ning, DONG Zaiwang. "CRC Look-up Table Optimization for Single-Bit Error Correction". In: TSINGHUA SCIENCE AND TECHNOLOGY ISSN 1007-0214 18/19 pp620-623 Volume 12, Number 5, October 2007.
  3. Johnston C A, Chao H J. "The ATM layer chip: An ASIC for BISDN applications". IEEE Journal on Selected Areas in Communications, 1991, 9(5): 741-750.
  4. Peterson, W. W. and Brown, D. T. "Cyclic Codes for Error Detection "Proceedings of the IRE 49: 228. doi: 10. 1109/JRPROC. 1961. 287814, January 1961.
  5. W. W Peterson, E. J. Weldon. "Cyclic Codes for Error Detection". Second Edition Published by MIT Press, 1972 ISBN 0262160390,9780262160391.
  6. Norman Matloff. "Cyclic Redundancy Checking".
  7. "Double Bits Error Correction Using CRC Method" by Shahram Babaie, Ahmad Khadem Zadeh, Seyed Hasan Es-hagi, Nima Jafari Navimipour. IN: Semantics, Knowledge and Grid, 2009. SKG 2009. Fifth International Conference. Oct. 2009, 254 – 257, 11050651.
  8. "FPGA implementation of one and two bit error correction using CRC" by Pramod S P, Akshay S kotain, Rajagopal A in International conference on recent trends in computer science and engineering 2012,ISBN 978-81-9089-807-2.
  9. Digital and analog communication systems, K. Sam Shanmugam, John Wiley, 1996.
  10. Giureppe Campobello, Giuseppe Patane. Marco Russo, "Parallel CRC Realization".
  11. T. V. Ramabadran and S. S. Gaitonde. "A tutorial on CRC computations". IEEE Micro, Vol. 8, No. 4, 1988, pp. 62-75.
  12. T. B. Pei and C. Zukowski "High-speed Parallel CRC Circuits in VLSI" IEEE Tran. on Communications,Vol. 40, April, 1992, pp 635-657
Index Terms

Computer Science
Information Sciences

Keywords

CRC Field Programmable Gate Array Single bit error correction Parallelism non-lookup technique

Powered by PhDFocusTM