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VLSI Implementation of Heterogeneous Adder for Performance Optimization
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 51 - Number 7 |
| Year of Publication: 2012 |
| Authors: Raminder Preet Pal Singh, Ashish Chaturvedi |
10.5120/8057-1405
|
Raminder Preet Pal Singh, Ashish Chaturvedi . VLSI Implementation of Heterogeneous Adder for Performance Optimization. International Journal of Computer Applications. 51, 7 ( August 2012), 37-40. DOI=10.5120/8057-1405
Abstract
An Adder is one of the significant hardware blocks in most digital systems such as digital signal processors and microprocessors etc. Over the last few decades lot of research have been carried out in order to design an efficient adder circuits in terms of compactness, high speed and low power consumption. However, area and speed are two conflict parameters. So, improving speed results always in larger area occupied by circuit on chip and vice-versa. In order to design an optimized adder circuit which provides area/delay tradeoffs, we studied different available parallel, synchronous adders and proposed a new adder based on combination of them. In this paper, we proposed a new type of adder architecture known as heterogeneous adder that consists of concatenation of sub-adder (homogeneous adder) of different types. The heterogeneous adder architecture provides better design tradeoffs in terms of area and delay characteristics.
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