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Analysis of Subthreshold Leakage Current in IP3 SRAM Bit-Cell under Temperature Variations in Deep-Submicrometer CMOS Technology
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 51 - Number 19 |
| Year of Publication: 2012 |
| Authors: Neeraj Kr. Shukla, Shilpi Birla, Saksham Dembla |
10.5120/8147-0272
|
Neeraj Kr. Shukla, Shilpi Birla, Saksham Dembla . Analysis of Subthreshold Leakage Current in IP3 SRAM Bit-Cell under Temperature Variations in Deep-Submicrometer CMOS Technology. International Journal of Computer Applications. 51, 19 ( August 2012), 1-4. DOI=10.5120/8147-0272
Abstract
In this paper, we present the analysis of subthreshold leakage current with temperature variations in an IP3 SRAM bit-cell. A comparison of subthreshold leakage current of IP3 SRAM bit-cell with conventional 6T, P4 and P3 is performed at elevated temperatures ranging from 00C to 1250C. It is observed that subthreshold leakage increases with temperature and also IP3 SRAM bit-cell has the lowest subthreshold leakage variations when compared with conventional 6T , P4 and P3 SRAM bit-cell structures.
References
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