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LPSR: Novel Low Power State Retention Technique for CMOS VLSI Design
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 51 - Number 18 |
| Year of Publication: 2012 |
| Authors: Rajani H.p., S. Y. Kulkarni |
10.5120/8145-1931
|
Rajani H.p., S. Y. Kulkarni . LPSR: Novel Low Power State Retention Technique for CMOS VLSI Design. International Journal of Computer Applications. 51, 18 ( August 2012), 42-49. DOI=10.5120/8145-1931
Abstract
In mobile computing and mobile communication applications powered by battery, the battery life is a premier concern. Leakage power loss is critical in CMOS VLSI circuits as it leaks the battery even when devices are in idle state. To reduce subthreshold leakage power as well as total power in CMOS logic gates and circuits a new circuit technique called LPSR Technique is proposed in this work. Earlier well known techniques for leakage reduction and state retention are compared with this technique. This technique reduces maximum amount of leakage power during deep sleep mode, maximum power reduction during dynamic (clocked) mode and has a provision of preserving state in low power sleep mode. All the circuits are designed, simulated and low power performance evaluation is done using 90nm CMOS technology files in Cadence Design Environment.
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