CFP last date
20 December 2024
Call for Paper
January Edition
IJCA solicits high quality original research papers for the upcoming January edition of the journal. The last date of research paper submission is 20 December 2024

Submit your paper
Know more
The week's pick
Responsive image
Improved Shuffled Frog Leaping Algorithm with Self-Adaptive Shuffling for Fuzzy Logic PD+G Controller Optimization in Robotic Manipulators

Duc Hoang Nguyen
Random Articles
Reseach Article

Architecture Design and FPGA Implementation of an FFT based Reactive Power Meter

by Msr Naidu, G.r Locharla, Gbsr Naidu
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 50 - Number 9
Year of Publication: 2012
Authors: Msr Naidu, G.r Locharla, Gbsr Naidu
10.5120/7801-0926

Msr Naidu, G.r Locharla, Gbsr Naidu . Architecture Design and FPGA Implementation of an FFT based Reactive Power Meter. International Journal of Computer Applications. 50, 9 ( July 2012), 32-34. DOI=10.5120/7801-0926

@article{ 10.5120/7801-0926,
author = { Msr Naidu, G.r Locharla, Gbsr Naidu },
title = { Architecture Design and FPGA Implementation of an FFT based Reactive Power Meter },
journal = { International Journal of Computer Applications },
issue_date = { July 2012 },
volume = { 50 },
number = { 9 },
month = { July },
year = { 2012 },
issn = { 0975-8887 },
pages = { 32-34 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume50/number9/7801-0926/ },
doi = { 10.5120/7801-0926 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:47:51.865556+05:30
%A Msr Naidu
%A G.r Locharla
%A Gbsr Naidu
%T Architecture Design and FPGA Implementation of an FFT based Reactive Power Meter
%J International Journal of Computer Applications
%@ 0975-8887
%V 50
%N 9
%P 32-34
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Reactive power measurement is increasingly paid attention by power industry. A novel architecture to measure the reactive power is proposed in this paper. Architecture is described in verilog and implemented using Xilinx ISE 13. 1i. In this method voltage and current signals in time domain are converted to the frequency domain and power on each component is calculated to obtain the total reactive power.

References
  1. S. A. Soliman, R. A. Alammari M. E. El-Hawary, "Effects of Harmonic Distortion on the Active and Reactive Power Measurements in theTime Domain: A Single Phase System. " 2001 IEEE Porto Power Tech Conference
  2. Leszek, s. Czarnecki, "Measurement of the Individual Harmonics Reactive Power in Nonsinusoidal Systems", IEEE Transactions On Instrumentation And Measurement.
  3. Jun Rongi, Gui-xin Zhangi "Electric Energy easurement in Digital Substation on A Number of Issues Discussed", CICED2008
  4. Branislav Djokic´, Senior Member, IEEE, "A High Performance Frequency Insensitive Quadrature Phase Shifter and Its Application in Reactive Power Measurements", IEEE Transactions On Instrumentation And Measurement.
  5. Elham B. Makram, Senior Member, IEEE "Effect of Harmonic Distortion in Reactive Power Measurement", IEEE Transactions on Industry Applications, vol. 28, no. 4, july / august 1992.
  6. Adalet N. Abiyev, Kamil Dimililer "Reactive Power Measurement in Sinusoidal and Nonsinusoidal Conditions by Use of the Walsh Functions", I2MTC 2008 - IEEE International Instrumentation and Measurement Technology Conference, Victoria, Vancouver Island, Canada, May 12-15, 2008
  7. AN-758, Application Note, Analog Devices, One Technology Way, P. O. Box 9106, Norwood, MA 02062-9106,Tel: 781/329-4700, Fax: 781/461-3113 www. analog. com
Index Terms

Computer Science
Information Sciences

Keywords

Xilinx FFT FPGA DFF

Powered by PhDFocusTM