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Optimization of Chip Interconnect Area by using Interconnect Length and Width

by Dr.Y.Venkatarami Reddy, D.Venkata Vara Prasad
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 5 - Number 3
Year of Publication: 2010
Authors: Dr.Y.Venkatarami Reddy, D.Venkata Vara Prasad
10.5120/897-1271

Dr.Y.Venkatarami Reddy, D.Venkata Vara Prasad . Optimization of Chip Interconnect Area by using Interconnect Length and Width. International Journal of Computer Applications. 5, 3 ( August 2010), 21-26. DOI=10.5120/897-1271

@article{ 10.5120/897-1271,
author = { Dr.Y.Venkatarami Reddy, D.Venkata Vara Prasad },
title = { Optimization of Chip Interconnect Area by using Interconnect Length and Width },
journal = { International Journal of Computer Applications },
issue_date = { August 2010 },
volume = { 5 },
number = { 3 },
month = { August },
year = { 2010 },
issn = { 0975-8887 },
pages = { 21-26 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume5/number3/897-1271/ },
doi = { 10.5120/897-1271 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T19:53:18.865301+05:30
%A Dr.Y.Venkatarami Reddy
%A D.Venkata Vara Prasad
%T Optimization of Chip Interconnect Area by using Interconnect Length and Width
%J International Journal of Computer Applications
%@ 0975-8887
%V 5
%N 3
%P 21-26
%D 2010
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents methodologies that provide better correlation between the apriori and posteriori estimation of interconnect length, width, area and power. A method to generate random realistic benchmark circuits for analysis is implemented. A prediction model that predicts the length, width, area and power of the benchmark circuit is developed. The net list is passed through the placement and routing phases to obtain the actual length. From the estimated length, the width, area and power are estimated. The effectiveness of the prediction technique used is validated from the results obtained. We postulate that the predicted area which comes out with a smaller error percentage than predicted length can be used as a termination condition in Simulated Annealing for placement. Results are compared for proving optimization with Lagrange’s Method.

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Index Terms

Computer Science
Information Sciences

Keywords

VLSI DSM FPGA

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