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Reseach Article

Performance Analysis of FTL Schemes

by M. N. Kale, A. S. Jahagirdar
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 48 - Number 19
Year of Publication: 2012
Authors: M. N. Kale, A. S. Jahagirdar
10.5120/7453-0271

M. N. Kale, A. S. Jahagirdar . Performance Analysis of FTL Schemes. International Journal of Computer Applications. 48, 19 ( June 2012), 1-6. DOI=10.5120/7453-0271

@article{ 10.5120/7453-0271,
author = { M. N. Kale, A. S. Jahagirdar },
title = { Performance Analysis of FTL Schemes },
journal = { International Journal of Computer Applications },
issue_date = { June 2012 },
volume = { 48 },
number = { 19 },
month = { June },
year = { 2012 },
issn = { 0975-8887 },
pages = { 1-6 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume48/number19/7453-0271/ },
doi = { 10.5120/7453-0271 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:44:28.638768+05:30
%A M. N. Kale
%A A. S. Jahagirdar
%T Performance Analysis of FTL Schemes
%J International Journal of Computer Applications
%@ 0975-8887
%V 48
%N 19
%P 1-6
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Today Nand Flash memory is not only used in hand hold electronic devices but also as secondary storage medium. It serves as an alternative to Hard Disk Drives (HDDs) in the form of Solid State Dives (SDDs). However, unlike HDD flash memory does not support in place update, i. e. for updating data, old data can not be replaced by new data. Data can be written only at clean i. e. already erased place. This is called as erase before update. This erase before update nature of Nand Flash memory is kept hidden with the help of a functionality called as address mapping or address translation. Many efforts for optimizing the working of address mapping schemes have been done by different research workers. Though various schemes are designed and proposed but there is no literature available providing mathematical computations comparing the performance of the various mapping schemes in the form of time complexity. In this paper we have tried to find out the comparative cost of block merge operation required during garbage collection for some representative mapping schemes like BAST [9] and FAST [7]. This paper also presents a review of all these schemes and presents a comparative trade offs among all these major schemes. The paper is divided into five sections: section 1 is introduction of Flash memory, section 2 describes various mapping schemes and presents their comparative performance, Section 3 does the conclusion. Section 4 is acknowledgement and section 5 describes the future scope.

References
  1. Yeonseung Ryu, "A Flash Translation Layer for NAND Flash-Based Multimedia Storage Devices", IEEE TRANSACTIONS ON MULTIMEDIA, pages: 563- 572, VOL. 13, NO. 3, JUNE 2011
  2. Shin I. : Light weight sector mapping scheme for NAND-based block devices, IEEE Transactions on Consumer Electronics, pages: 651 – 656, May 2010, ISSN: 0098-3063 Volume: 56 Issue:2
  3. A. Gupta, Y. Kim, and B. Urgaonkar, "DFTL: a Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings," in ASPLOS, 2009.
  4. Aayush Gupta Youngjae Kim Bhuvan Urgaonkar "DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings" Computer Systems Laboratory, Department of Computer Science and Engineering. The Pennsylvania State University, University Park, PA 16802, Technical Report CSE-08-012August 2008
  5. Dongchul Park, Biplob Debnath, and David Du "CFTL: A Convertible Flash Translation Layer with Consideration of Data Access Patterns", Technical Report Department of Computer Science and Engineering University of Minnesota September 14, 2009.
  6. S. Lee, D. Shin, Y. Kim, and J. Kim. LAST: Locality-Aware Sector Translation for NAND Flash Memory-Based Storage Systems, in Proceedings of the International Workshop on Storage and I/O Virtualization, Performance, Energy, Evaluation and Dependability (SPEED2008), February 2008.
  7. S. Lee, D. Park, T. Chung, D. Lee, S. Park, and H. Song. A Log Buffer based Flash Translation Layer Using Fully Asso-ciative Sector Translation. IEEE Transactions on Embedded Computing Systems, 6(3):18, 2007. ISSN 1539–9087.
  8. J. Kang, H. Jo, J. Kim, and J. Lee. A Superblock-based Flash Translation Layer for NAND Flash Memory. In Proceedings of the International Conference on Embedded Software (EM-SOFT), pages 161–170, October 2006. ISBN 1-59593-542-8.
  9. Chung, D. Park, S . Park, D. Lee, S. Lee, and H. Song. System Software for Flash Memory: A Survey. In Proceedings of the International Conference on Embedded and Ubiquitous Computing, pages 394–404, August 2006.
  10. JFFS : The Journalling Flash File System David Woodhouse Red Hat, Inc. dwmw2@cambridge. redhat. com
  11. Yang Hu "Achieving Page-Mapping FTL Performance at Block-Mapping FTL Cost by Hiding Address Translation(HAT)" Huazhong University of Sci. & Tech. China
  12. Micron Technical Report (TN-29-07): Small-Block vs. Large-Block NAND Flash Devices. Technical Report (TN-29-07): Small-Block vs. Large-Block NAND Flash Devices.
  13. Micron Technical Report (TN-29-07): Small-Block vs. Large-Block NAND Flash Devices. Technical Report (TN-29-07): Wear-Leveling Techniques in NAND Flash Devices.
Index Terms

Computer Science
Information Sciences

Keywords

Ftl: Flash Translation Layer Page Mapping