International Journal of Computer Applications |
Foundation of Computer Science (FCS), NY, USA |
Volume 48 - Number 19 |
Year of Publication: 2012 |
Authors: M. N. Kale, A. S. Jahagirdar |
10.5120/7453-0271 |
M. N. Kale, A. S. Jahagirdar . Performance Analysis of FTL Schemes. International Journal of Computer Applications. 48, 19 ( June 2012), 1-6. DOI=10.5120/7453-0271
Today Nand Flash memory is not only used in hand hold electronic devices but also as secondary storage medium. It serves as an alternative to Hard Disk Drives (HDDs) in the form of Solid State Dives (SDDs). However, unlike HDD flash memory does not support in place update, i. e. for updating data, old data can not be replaced by new data. Data can be written only at clean i. e. already erased place. This is called as erase before update. This erase before update nature of Nand Flash memory is kept hidden with the help of a functionality called as address mapping or address translation. Many efforts for optimizing the working of address mapping schemes have been done by different research workers. Though various schemes are designed and proposed but there is no literature available providing mathematical computations comparing the performance of the various mapping schemes in the form of time complexity. In this paper we have tried to find out the comparative cost of block merge operation required during garbage collection for some representative mapping schemes like BAST [9] and FAST [7]. This paper also presents a review of all these schemes and presents a comparative trade offs among all these major schemes. The paper is divided into five sections: section 1 is introduction of Flash memory, section 2 describes various mapping schemes and presents their comparative performance, Section 3 does the conclusion. Section 4 is acknowledgement and section 5 describes the future scope.