We apologize for a recent technical issue with our email system, which temporarily affected account activations. Accounts have now been activated. Authors may proceed with paper submissions. PhDFocusTM
CFP last date
20 December 2024
Reseach Article

Energy Efficient Fully Associative Cache Model

by S. Subha
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 47 - Number 6
Year of Publication: 2012
Authors: S. Subha
10.5120/7192-9949

S. Subha . Energy Efficient Fully Associative Cache Model. International Journal of Computer Applications. 47, 6 ( June 2012), 16-18. DOI=10.5120/7192-9949

@article{ 10.5120/7192-9949,
author = { S. Subha },
title = { Energy Efficient Fully Associative Cache Model },
journal = { International Journal of Computer Applications },
issue_date = { June 2012 },
volume = { 47 },
number = { 6 },
month = { June },
year = { 2012 },
issn = { 0975-8887 },
pages = { 16-18 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume47/number6/7192-9949/ },
doi = { 10.5120/7192-9949 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:41:11.256459+05:30
%A S. Subha
%T Energy Efficient Fully Associative Cache Model
%J International Journal of Computer Applications
%@ 0975-8887
%V 47
%N 6
%P 16-18
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Energy consumption in caches depends on the number of enabled sets/ways/blocks. The optimal energy consumption is the case of one set/one way/one block enabled. This paper proposes an algorithm to map cache line to one block in fully associative cache by XOR'ing the address with constant. Bit selection is applied to the result and the block accessed. Only one block is accessed in this mapping. The proposed model is simulated with SPEC2K benchmarks. The average memory access time is comparable with traditional fully associative cache with energy savings.

References
  1. A. J. Smith, Cache memories, ACM Computing Surveys, Vol. 14 No. 3, pp. 473-530, September 1982
  2. Antonio Gonzalez, Mateo Valero, Nigel Topham, Joan. M. Parcerisa, Eliminating Cache Conflict Misses Through XOR-Based Placement Functions, Proceedings of International Conference on Supercomputing, 1997, pp. 76-83
  3. Chuanjun Zhang, Frank Vahid, Jun Yang and Walid Najjar, A Way-Halting Cache for Low-Energy High Performance Systems, ACM Transactions on Architecture and Code Optimization, Vol. 2, No. 1, March 2003, pp. 34-54
  4. David. A. Patterson and John. L. Hennessy, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, 3rd Edition, 2003
  5. David. H. Albonesi, Selective Cache Ways: On demand cache resource Allocation, Proceedings of International Symposium on Microarchitecture, 1999
  6. G. Rivera, C. W. Tseng, Data Transformations for Eliminating Conflict Misses, PLDI, 1998
  7. Huiyang Zhou, Mark. C. Toburen, Eric Rotenberg, Thomas. M. Conte, Adaptive Mode Control: A Static-Power-Efficient Cache Design, ACM Transactions on Embedded Computing Systems, Vol. 2, No. 3, August 2003, pp. 347-372
  8. Jung-Wook Park, Gi-Ho Park, Sung-Bae Park, Shin-Dug Kim, Power-aware deterministic block allocation for low-power way-selective cache structure, Proceedings of ICCD, 2004
  9. Michael. D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy, Reducing set-associative cache energy via way-prediction and selective direct mapping, Proceedings of MICRO, 2001
  10. RuiMin, Zhiyong Xu, Yiming Hu, Wen-ben Jone, Partial tag comparison: a new technology for power-efficient set-associative cache designs, Proceedings of 17th International Conference on VLSI Design, 2004, pp. 183-188
  11. S. Kim, N. Vijaykrishnan, M. Kandemir, A. Sivasubramaniam, M. J. Irwin, E. Geethanjali, Power-aware partitioned cache architectures, Proceedings of ISPLED, 2001, pp. 64-67
  12. S. Subha, Set Associative Cache Model with Energy Saving, Proceedings of ITNG, 2008, pp. 1249-1250
  13. S. Subha, An Algorithm for Fully Associative Cache Memory, Proceedings of Second Bihar Science Conference, 2009
  14. S. Subha, Performance Analysis of Variable number of Sets in Fully Associative Cache, Proceedings of ICC, 2009, pp. 295-298
  15. Zhigang Hu, Stefanos Kaxiras, Margaret Martonosi, Improving Cache Power Efficiency with an Asymmetric Set Associative Cache, Proceedings of Workshop of Memory Performance, 2001
Index Terms

Computer Science
Information Sciences

Keywords

Energy Consumption Fully Associative Cache Xor Logic