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Implementation of Low Power Parallel Compressor for Multiplier using Self Resetting Logic

by Suparshya Babu Sukhavasi, Susrutha Babu Sukhavasi, Vijaya Bhaskar Madivada, Habibulla Khan, S R Sastry Kalavakolanu
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 47 - Number 3
Year of Publication: 2012
Authors: Suparshya Babu Sukhavasi, Susrutha Babu Sukhavasi, Vijaya Bhaskar Madivada, Habibulla Khan, S R Sastry Kalavakolanu
10.5120/7169-9750

Suparshya Babu Sukhavasi, Susrutha Babu Sukhavasi, Vijaya Bhaskar Madivada, Habibulla Khan, S R Sastry Kalavakolanu . Implementation of Low Power Parallel Compressor for Multiplier using Self Resetting Logic. International Journal of Computer Applications. 47, 3 ( June 2012), 27-32. DOI=10.5120/7169-9750

@article{ 10.5120/7169-9750,
author = { Suparshya Babu Sukhavasi, Susrutha Babu Sukhavasi, Vijaya Bhaskar Madivada, Habibulla Khan, S R Sastry Kalavakolanu },
title = { Implementation of Low Power Parallel Compressor for Multiplier using Self Resetting Logic },
journal = { International Journal of Computer Applications },
issue_date = { June 2012 },
volume = { 47 },
number = { 3 },
month = { June },
year = { 2012 },
issn = { 0975-8887 },
pages = { 27-32 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume47/number3/7169-9750/ },
doi = { 10.5120/7169-9750 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:40:56.587917+05:30
%A Suparshya Babu Sukhavasi
%A Susrutha Babu Sukhavasi
%A Vijaya Bhaskar Madivada
%A Habibulla Khan
%A S R Sastry Kalavakolanu
%T Implementation of Low Power Parallel Compressor for Multiplier using Self Resetting Logic
%J International Journal of Computer Applications
%@ 0975-8887
%V 47
%N 3
%P 27-32
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper a new approach of reducing power for a given system is developed that is self resetting logic, a parallel compressor is developed for multiplier by reducing its power with facilitation of this low power logic technique. By using this technique the power dissipation is significantly reduced with respect to other logics. By implementing the parallel compressor the performance of the circuit is increases.

References
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Index Terms

Computer Science
Information Sciences

Keywords

High Speed Vlsi Self-resetting Logic (srl) Topologies Power Dissipation

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