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Analysis and Comparison Dynamic Power Consumption of 8-Bit Multipliers for Low Power Application

by B. Sathiyabama, S. Malarkkan
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 46 - Number 16
Year of Publication: 2012
Authors: B. Sathiyabama, S. Malarkkan
10.5120/6993-9472

B. Sathiyabama, S. Malarkkan . Analysis and Comparison Dynamic Power Consumption of 8-Bit Multipliers for Low Power Application. International Journal of Computer Applications. 46, 16 ( May 2012), 16-20. DOI=10.5120/6993-9472

@article{ 10.5120/6993-9472,
author = { B. Sathiyabama, S. Malarkkan },
title = { Analysis and Comparison Dynamic Power Consumption of 8-Bit Multipliers for Low Power Application },
journal = { International Journal of Computer Applications },
issue_date = { May 2012 },
volume = { 46 },
number = { 16 },
month = { May },
year = { 2012 },
issn = { 0975-8887 },
pages = { 16-20 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume46/number16/6993-9472/ },
doi = { 10.5120/6993-9472 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:39:54.427981+05:30
%A B. Sathiyabama
%A S. Malarkkan
%T Analysis and Comparison Dynamic Power Consumption of 8-Bit Multipliers for Low Power Application
%J International Journal of Computer Applications
%@ 0975-8887
%V 46
%N 16
%P 16-20
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Multipliers and adders are the most significant part of all data path circuits in the microprocessor and digital signal processor. The power and speed of the multiplier and adder affects the entire performance of the system. In this paper, low power multiplier using Hybrid adder is proposed. Also it presents the analysis of three modified multipliers: Braun array multiplier, Baugh Wooley array multiplier, and CSA Multiplier with optimized adders. The multipliers are designed with optimized Hybrid and other adders using transistor sizing technique. The performance of power and delay of the multipliers are analyzed with optimization. All circuits are implemented in HSPICE BSIM model at 90nm deep submicron technology

References
  1. Massoud Pedram. , 1995 Design Technologies for Low Power VLSI, Encyclopedia of Computer Science and Technology,
  2. Gray Yeap and Gilbert, 1998 Practical Low power Digital VLSI Design, Kluwer Academic Publishers.
  3. Rabaey. J, 2003 Digital Integrated Circuits: A Design Perspective, 2nd edition, Prentice-Hall.
  4. Pedram, . 1996,Power Minimization in IC Design, ACM Transactions on Design Automation of Electronic Systems, Vol 1, No. 1, pp. 3-56
  5. Jui-Ming Chang and Massoud Pedram. 1997,Energy Minimization Using Multiple Supply Voltages", IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 5, No. 4, Pp: 436-444,
  6. J. P. Fishburn and A. E. Dunlop, 1985, TILOS: a posynomial programming approach to transistor sizing," in Proceedingsof the International Conference on computer Aided Design(ICCAD '85),
  7. Nikoubin, T. , Pouri, S. , Bahrebar, P. , and Navi, N. , 2007. A New Transistor Sizing Algorithm for Balanced XOR/XNOR Circuits,12th International CSI Computer Conference, CSICC
  8. Zhuang. N and Wu. H, ,1992 A New Design of the CMOS Full Adder, IEEE J. Solid State Circuits, vol. 27, no. 5, pp. 840-844
  9. Shalem R, John E, John L. K, 1999 A novel low-power energy recovery full adder cell, in: Proceedings of the Great Lakes Symposium on VLSI, pp. 380–383.
  10. Alioto M, Palumbo G, 2002 Analysis and comparison of the full adder block, IEEE Trans. VLSI 10 . pp806–823.
  11. Wey K. C. , Huang C. H and Chow H. C, . 2002 A New Low-Voltage CMOS 1-Bit Full Adder for High Performance Applications, IEEE, pp. 21- 24
  12. H. T. Bui, Y. Wang, and Y. Jiang 2002 Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates," IEEE Trans. on Circuits and Systems-I/: Analog and digital signal processing, vol. 49, no. 1, pp. 25-30.
  13. Chang C. H, Gu J, Zhang M, 2005 A review of 0. 18-µm full adder Performances for tree structured arithmetic circuits," IEEE Trans. Very Large Scale Integration System. vol. 13, pp 686-695.
  14. Sameer Goel, Ashok Kumar, and M. A. Bayoumi, 2006 Design of Robust Energy Efficient Full Adders for Deep Sub micrometer Design Using Hybrid -CMOS Logic Style", IEEE Trans. On VLSI Systems, vol. 14, no. 12.
  15. Massimo Alioto, Gaetano Palumbo, Analysis and Comparison on Full Adder Block in Submicron Technology, IEEE TRANS, ON VL SI SYSTEMS, Vol. 10, No. 6, December,Pp 806-822
  16. B. Sathiyabama S. Malarkkan, 2012 Low Power Novel Hybrid Adders For Datapath Circuits In DSP Processor, Indian Journal on computer Science and Engineering, vol 3,No 1, ,pp 162-167,
  17. B. Sathiyabama S. Malarkkan , 2012Reduction in Dynamic Power of Adders for DSP using Technology Scaling, proceeding on EXCITE 2012. pp 1-5
  18. C. Senthil pari et al. 2008 Design of a low power high performance 8_8 multiplier using a Shannon-based adder cell Shannon-based adder cell,Micro electronics journal,pp812-821
Index Terms

Computer Science
Information Sciences

Keywords

Dynamic Power Cmosfa Lpfa Tgfa Tgdcfa Sfa Cpl

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