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FPGA Implementation of Low Power Hardware Efficient Flagged Binary Coded Decimal Adder
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 46 - Number 14 |
| Year of Publication: 2012 |
| Authors: K. N. Vijeyakumar, V.sumathy, A.dinesh Babu, S.elango, S.saravanakumar |
10.5120/6981-9614
|
K. N. Vijeyakumar, V.sumathy, A.dinesh Babu, S.elango, S.saravanakumar . FPGA Implementation of Low Power Hardware Efficient Flagged Binary Coded Decimal Adder. International Journal of Computer Applications. 46, 14 ( May 2012), 41-45. DOI=10.5120/6981-9614
Abstract
This paper presents a novel architecture for hardware efficient binary represented decimal addition. We extend the two operand ripple carry addition by one with the third input being constant. The addition technique is made fast by generating flag bits appropriate to the constant added. The third constant in case of our proposed design is 6(0110) for converting the outputs exceeding 9 to Binary Coded Decimal (BCD) number. The proposed BCD adder has been designed using VHDL code and synthesized using Altera Quartus II. Experimental results show that the proposed design outperforms the previous researches in terms of power dissipation and area.
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