The week's pick
Random Articles
Reseach Article
A High Speed Parallel Counter Architecture and its Implementation in Programmable Square Finder cum Frequency Divider Circuit
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 46 - Number 12 |
| Year of Publication: 2012 |
| Authors: Pramod.p |
10.5120/6961-9457
|
Pramod.p . A High Speed Parallel Counter Architecture and its Implementation in Programmable Square Finder cum Frequency Divider Circuit. International Journal of Computer Applications. 46, 12 ( May 2012), 22-27. DOI=10.5120/6961-9457
Abstract
An 8-bit programmable square finder cum frequency divider architecture is presented. This special architecture includes a high speed parallel counter, clock trigger circuit, eight bit multiplier logic, sequence termination logic and sequence restarter logic. The entire architecture is divided into two parts: The frequency divider section and the square finder section. The frequency divider circuit outputs a sequence of states and the modulus is determined by the external frequency select input. The Square finder circuit finds the square of the given number by repetitively adding the number that much times. The counter consists of two main sections- the counting section and the state Anticipation Module. The 8-bit square finder cum frequency divider employing existing counter architecture [5] consumes a total transistor count of 1206 whereas the same using proposed counter architecture consumes only 1038. The worst case delay of the proposed programmable square finder cum frequency divider architecture employing the existing and proposed counter architecture was found to be 21. 829ns and 20. 686 respectively and the Power dissipation at 250 MHz was found to be 6. 35 mW and 5. 77mW respectively.
References
- Chu, D. "Phase digitizing sharpens timing measurements," IEEE Spect. , pp. 28-32, July 1988
- Yuan, J. R. "Efficient CMOS Counter Circuits," Electronics Letters,vol. 24, pp. 1,311-1,313, Oct. 1988.
- Yuan, J. R. and Svensson, C. "Fast CMOS Nonbinary Divider and Counter," Electronics Letters, vol. 29, pp. 1,222-1,223, June 1993.
- Rogenmoser, R. , Huang, Q and Piazza, F "1. 57 GHz Asynchronous and 1. 4 GHz Dual-Modulus 1. 2 mm CMOS Prescalers," Proc. Custom Integrated Circuits Conf. , pp. 387-390, May 1994.
- Abdel Hafeez, S and Ann Gordon Ross,"A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic", IEEE Transactions on Very Large Scale Integration(VLSI) Systems, vol. 19, no. June2011
- Abdel-Hafeez, S Harb. S, and Eisenstadt. W, "High speed digital CMOS divide-by-N frequency divider," in Proc. IEEE Int. Symp. Circuits Syst. , pp. 592–595,2008
- Alioto, M. Mita. R, and Palumbo. G,"Design of high-speed power-efficient MOS current-mode logic frequency dividers," IEEE Trans. Circuits Syst. II, Expr. Briefs, vol. 53, no. 11, pp. 1165–1169, 2006
- Chang, B Park. J, and Kim. W, "A 1. 2 GHz CMOS dual-modulus prescalar using new dynamic D-type flip-flops," IEEE J. Solid-State Circuits, vol. 31, no. 5, pp. 749–75, 1996
- Hendry. D. C, "Sequential lookahead method for digital counters," IEEE Electron. Lett. , vol. 32, no. 3, pp. 160–161,1996.
- Kakarountas, A. P. , Theodoridis, G. , Papadomanolakis K. S. and C. E. Goutis, "A novel high-speed counter with counting rate independent of the counter's length," in Proc. IEEE Int. Conf. Electron. , Circuits Syst. (ICECS), UAE, Dec. 2003, pp. 1164–1167
- Altera Corp. , Santa Clara, CA, "FLEX8000, field programmable gate array logic device," 2008.
- Stan, M. R. , "Systolic counters with unique zero state," in Proc. IEEE Proc. Int. Symp. Circuits Syst. (ISCAS), 2004, pp. II-909–II-912.
- Yamamoto, K and Fujishima, M, "4. 3 GHz 44 uW CMOS frequency divider," in Proc. IEEE Int. Solid-State Circuits Conf. , 2004, pp. 104–105.
- Alioto, M. and Palumbo, G. , "Model and Design of Bipolar and MOSCurrent-Mode Logic: CML, ECL and SCL Digital Circuits". Norwell,MA: Springer-Verlag, 2005.
Index Terms
Keywords