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Low Power and Small Area Implementation for OFDM Applications
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 45 - Number 9 |
| Year of Publication: 2012 |
| Authors: K. Umapathy, D. Rajaveerappa |
10.5120/6810-9158
|
K. Umapathy, D. Rajaveerappa . Low Power and Small Area Implementation for OFDM Applications. International Journal of Computer Applications. 45, 9 ( May 2012), 35-38. DOI=10.5120/6810-9158
Abstract
This paper proposes that several FFT algorithms such as radix-2, radix-4 and split radix were designed using VHDL with the multiplication complexity reduced more than 30% by using the newly proposed CSD constant multipliers instead of the programmable multipliers and the simulations of standard 0. 35 ?m. The sizes of FFT/IFFT operations are varied in different applications of OFDM systems. The reorganized Mixed Radix 4-2 Butterfly FFT with bit reversal for the output sequence derived by index decomposition execution is our suggested VLSI system architecture to design the module FFT/IFFT processor for OFDM systems. The output shows that the proposed processor architecture can minimize the area cost while keeping a high-speed processing speed, a decrement of more than 70% of the power consumption/area when compared with complex multiplier
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