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DSTN (Distributed Sleep Transistor Network) for Low Power Programmable Logic array Design

by Pradeep Singla, Kamya Dhingra, Naveen Kr. Malik
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 45 - Number 17
Year of Publication: 2012
Authors: Pradeep Singla, Kamya Dhingra, Naveen Kr. Malik
10.5120/7004-9563

Pradeep Singla, Kamya Dhingra, Naveen Kr. Malik . DSTN (Distributed Sleep Transistor Network) for Low Power Programmable Logic array Design. International Journal of Computer Applications. 45, 17 ( May 2012), 31-36. DOI=10.5120/7004-9563

@article{ 10.5120/7004-9563,
author = { Pradeep Singla, Kamya Dhingra, Naveen Kr. Malik },
title = { DSTN (Distributed Sleep Transistor Network) for Low Power Programmable Logic array Design },
journal = { International Journal of Computer Applications },
issue_date = { May 2012 },
volume = { 45 },
number = { 17 },
month = { May },
year = { 2012 },
issn = { 0975-8887 },
pages = { 31-36 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume45/number17/7004-9563/ },
doi = { 10.5120/7004-9563 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:37:52.821907+05:30
%A Pradeep Singla
%A Kamya Dhingra
%A Naveen Kr. Malik
%T DSTN (Distributed Sleep Transistor Network) for Low Power Programmable Logic array Design
%J International Journal of Computer Applications
%@ 0975-8887
%V 45
%N 17
%P 31-36
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

With the high demand of the portable electronic products, Low- power design of VLSI circuits & Power dissipation has been recognized as a challenging technology in the recent years. PLA (Programming logic array) is one of the important off shelf part in the industrial application. This paper describes the new design of PLA using power gating structure sleep transistor at circuit level implementation for the low power applications. The important part of the power gating design i. e. header and footer switch selection is also describes in the paper. The simulating results of the proposed architecture of the new PLA is shown and compared with the conventional PLA. This paper clearly shows the optimization in the reduction of power dissipation in the new design implementation of the PLA. The transient response of the power gates structure of PLA is also illustrate in the paper by using TINA-PRO software.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Low Power Design Sleep Transistor Header Footer Power Gating Tina- Pro Pla

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