We apologize for a recent technical issue with our email system, which temporarily affected account activations. Accounts have now been activated. Authors may proceed with paper submissions. PhDFocusTM
CFP last date
20 November 2024
Call for Paper
December Edition
IJCA solicits high quality original research papers for the upcoming December edition of the journal. The last date of research paper submission is 20 November 2024

Submit your paper
Know more
The week's pick
Responsive image
Improved Shuffled Frog Leaping Algorithm with Self-Adaptive Shuffling for Fuzzy Logic PD+G Controller Optimization in Robotic Manipulators

Duc Hoang Nguyen
Random Articles
Reseach Article

Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block Chaining concept using Verilog and FPGA

by Aqib Al Azad
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 44 - Number 16
Year of Publication: 2012
Authors: Aqib Al Azad
10.5120/6345-8380

Aqib Al Azad . Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block Chaining concept using Verilog and FPGA. International Journal of Computer Applications. 44, 16 ( April 2012), 6-15. DOI=10.5120/6345-8380

@article{ 10.5120/6345-8380,
author = { Aqib Al Azad },
title = { Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block Chaining concept using Verilog and FPGA },
journal = { International Journal of Computer Applications },
issue_date = { April 2012 },
volume = { 44 },
number = { 16 },
month = { April },
year = { 2012 },
issn = { 0975-8887 },
pages = { 6-15 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume44/number16/6345-8380/ },
doi = { 10.5120/6345-8380 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:35:42.114215+05:30
%A Aqib Al Azad
%T Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block Chaining concept using Verilog and FPGA
%J International Journal of Computer Applications
%@ 0975-8887
%V 44
%N 16
%P 6-15
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper, Data Encryption Standard (DES) and Triple Data Encryption Standard (TDES) algorithm and their efficient hardware implementation in cyclone II Field Programmable Gate Array (FPGA) is analyzed with the help of Cipher Block Chaining (CBC) concept. The Data Encryption Standard (DES) has been the most extensively used encryption algorithm in recent times. Triple DES is the common name for the Triple Data Encryption Algorithm (TDEA or Triple DEA) block cipher, which applies the Data Encryption Standard (DES) cipher algorithm three times to each data block. The paper covers DES and Triple DES algorithm with Cipher Block Chaining concept, simulation results, basic FPGA technology and the implementation details of the proposed DES and Triple DES architecture. Register transfer level (RTL) of DES and Triple DES algorithm is designed, simulated and implemented separately using Verilog in different FPGA devices including Cyclone II, Spartan 3E, Vertex 5 and Vertex E series FPGAs. The results from the comparison with existing implementations show that the proposed design was efficient in all aspects

References
  1. "Data encryption standard (DES) ", National Bureau of Standards (U. S. ), Federal Information Processing Standards Publication 46, National Technical Information Service,Springfield, VA,Apr. 1977.
  2. W. Stallings, Cryptography and Network Security: Principles and Practice, 4th ed , Prentice-Hall, 2006.
  3. K. Wong, "A single-chip FPGA implementation of the data encryption standard (des) algorithm" IEEE 1998 pp 827-832.
  4. F. Hoornaert, J. Goubert, and Y. Desmedt, "Efficient hardware implementation of the DES," in Proc. Adv. Cryptol. (CRYPTO'84), 1984, pp. 147–173.
  5. A. Dhir "Data Encryption using DES/Triple-DES Functionality in Spartan-II FPGAs", White Paper: Spartan-II FPGAs, WP115 (v1. 0) March 9, 2000.
  6. P. Ghosal and M. Biswas, "A Compact FPGA Implementation of Triple-DES Encryption System with IP Core Generation and On-Chip Verification", International Conference on Industrial Engineering and Operations Management, 2010.
  7. F. Antonios, P. Nikolaos, M. Panagiotis, and A. Emmanouel, "Hardware Implementation of Triple-DES Encryption/ Decryption Algorithm", International Conference on Telecommunications and Multimedia, 2006.
  8. T. Schaffer, A. Glaser, and P. D. Franzon, "Chip-package co-implementation of a triple DES processor," IEEE Transactions on Advanced Packaging, pp. 194-202, Feb. 2004.
  9. Freesoft. (2011). Block Ciphers. Retrieved November 20, 2011, from http://www. freesoft. org/CIE/Topics/143. htm.
  10. Wikipedia. (2011). Data Encryption Standard. Retrieved November 20, 2011, from http://en. wikipedia. org/wiki/Data_Encryption_Standard.
  11. Wikipedia. (2011). Triple DES. Retrieved November 20, 2011, from http://en. wikipedia. org/wiki/Triple_DES.
  12. C. Boyd. "Modern Data Encryption," Electronics & Communication Engineering Journal, October 1993, pp 271-278.
  13. W. Diffie, "Cryptographic Technology: Fifteen Year Forecast" Reprinted by permission AAAS, 1982 from Secure Communications and Asymmetric Crypto Systems. AAAS Selecte8 Symposia. Editor: C. J. Simmons. Vol. 69, Westview Press, Boulder, Colorado, pp 38-57.
Index Terms

Computer Science
Information Sciences

Keywords

Cbc Fpga Des Tdes Rtl Verilog

Powered by PhDFocusTM