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Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block Chaining concept using Verilog and FPGA

by Aqib Al Azad
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 44 - Number 16
Year of Publication: 2012
Authors: Aqib Al Azad
10.5120/6345-8380

Aqib Al Azad . Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block Chaining concept using Verilog and FPGA. International Journal of Computer Applications. 44, 16 ( April 2012), 6-15. DOI=10.5120/6345-8380

@article{ 10.5120/6345-8380,
author = { Aqib Al Azad },
title = { Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block Chaining concept using Verilog and FPGA },
journal = { International Journal of Computer Applications },
issue_date = { April 2012 },
volume = { 44 },
number = { 16 },
month = { April },
year = { 2012 },
issn = { 0975-8887 },
pages = { 6-15 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume44/number16/6345-8380/ },
doi = { 10.5120/6345-8380 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T20:35:42.114215+05:30
%A Aqib Al Azad
%T Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher Block Chaining concept using Verilog and FPGA
%J International Journal of Computer Applications
%@ 0975-8887
%V 44
%N 16
%P 6-15
%D 2012
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper, Data Encryption Standard (DES) and Triple Data Encryption Standard (TDES) algorithm and their efficient hardware implementation in cyclone II Field Programmable Gate Array (FPGA) is analyzed with the help of Cipher Block Chaining (CBC) concept. The Data Encryption Standard (DES) has been the most extensively used encryption algorithm in recent times. Triple DES is the common name for the Triple Data Encryption Algorithm (TDEA or Triple DEA) block cipher, which applies the Data Encryption Standard (DES) cipher algorithm three times to each data block. The paper covers DES and Triple DES algorithm with Cipher Block Chaining concept, simulation results, basic FPGA technology and the implementation details of the proposed DES and Triple DES architecture. Register transfer level (RTL) of DES and Triple DES algorithm is designed, simulated and implemented separately using Verilog in different FPGA devices including Cyclone II, Spartan 3E, Vertex 5 and Vertex E series FPGAs. The results from the comparison with existing implementations show that the proposed design was efficient in all aspects

References
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Index Terms

Computer Science
Information Sciences

Keywords

Cbc Fpga Des Tdes Rtl Verilog

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