The week's pick
Reseach Article
Modified Booth Multiplier with Carry Select Adder using 3-stage Pipelining Technique
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 44 - Number 14 |
| Year of Publication: 2012 |
| Authors: Kulvir Singh, Dilip Kumar |
10.5120/6334-8710
|
Kulvir Singh, Dilip Kumar . Modified Booth Multiplier with Carry Select Adder using 3-stage Pipelining Technique. International Journal of Computer Applications. 44, 14 ( April 2012), 35-38. DOI=10.5120/6334-8710
Abstract
This paper presents a high-speed and low area 16 ×16 bit Modified Booth Multiplier (MBM) by using Carry Select Adder (CSA) and 3-stage pipelining technique. CSA improves the performance of MBM and pipelining technique reduces the delay time. Using these techniques, the delay is reduced by 56% and the numbers of SLICES and LUT's are reduced by 4% as compared to high speed MBM. The multiplier circuit is designed using VHDL and simulated using Xilinx ISE Simulator. The power metric of the MBM is evaluated using Cadence tools
References
- Wen-Chang Yeh and Chein-Wei Jen, "High-speed Booth encoded parallel multiplier design", IEEE Transaction on Computers, vol. 49, pp. 692-701, July 2000.
- Hwang-Cherng Chow and I-Chyn Wey, "A 3. 3V 1GHz high speed pipelined Booth multiplier", Proceedings of IEEE ISCAS, vol. 1, pp. 457-460. ,May 2002 .
- S. B. Tatapudi and J. G. Delgado-Frias, "Designing pipelined systems with a clock period Approaching pipeline register delay," Proceedings of IEEE MWSCAS, vol. 1, pp. 871-874, Aug. 2005.
- A. D. Booth, "A signed binary multiplication technique", Quarterly J. Mechanical and Applied Math, vol. 4, pp. 236-240, 1951.
- W. C. Yen and C. W. Jen, "High-speed booth encoded parallel multiplier design," IEEE Transaction on Computers , vol. 49, pp. 692–701, Jul. 2000.
- C. S. Wallace, "A suggestion for parallel multipliers", IEEE Transaction on Electron and Computers, vol. 13, pp. 14–17, Feb. 1964.
- J. Fadavi-Ardekani, "M × N booth encoded multiplier generator using optimized Wallace trees", IEEE Transaction on Very Large Scale Integration (VLSI) System, vol. 1, pp. 120–125, 1993.
- P. J. ; De Michelli, G. , "Circuit and Architecture Trade for High-Speed Multiplication", IEEE Journal Solid State Circuits, vol. 26, pp. 1184-1198, Sept. 1991.
- V. Oklobdzija, "High-Speed VLSI Arithmetic Units: Adders and Multipliers in Design of High-Performance Microprocessor Circuits", Book Chapter, Book edited by A Chandrakasan, IEEE Press, 2000.
- Soojin Kim and Kyeongsoon Cho. , "Design of High-speed Modified Booth Multipliers Operating at GHz Ranges", World Academy of Science, Engineering and Technology, 2010.
- B. Ramkumar and Harish M Kittur, "Low-Power and Area-Efficient Carry Select Adder", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, pp. 371-375, Feb. 2012.
Index Terms
Keywords