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Design and Implementation of Pipeline Architecture for High Performance 2-D Daubechies Wavelet Transform
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 43 - Number 24 |
| Year of Publication: 2012 |
| Authors: T. Dhanya, V. Nagarajan |
10.5120/6436-8818
|
T. Dhanya, V. Nagarajan . Design and Implementation of Pipeline Architecture for High Performance 2-D Daubechies Wavelet Transform. International Journal of Computer Applications. 43, 24 ( April 2012), 11-14. DOI=10.5120/6436-8818
Abstract
Wavelet Transforms are used in number of application. They are applied in different fields such as signal processing, speech and image compression, biometrics, and so on. One of its important applications is image compression. Wavelet Transforms are preferred over other transforms, to compress image, since reconstruction is more accurate. Design of discrete wavelet transforms is complex due to large number of arithmetic operations involved. In this paper, pipeline VLSI architecture for the computation of the 2-D discrete wavelet transform (DWT) using db2 filter is proposed. The main focus of the scheme is to reduce the number of clock cycles needed for the computation. The hardware resources needed is optimized by maximizing the inter- and intra-stage parallelisms of the pipeline. The inter-stage parallelism is enhanced by optimally mapping a level of decomposition to the stages of the pipeline. The intra-stage parallelism is enhanced by decomposing the filtering operation equally into two subtasks that can be executed independently in parallel so that the delay of the critical data path for the filtering operation is minimized. This architecture requires smaller number of clock cycles and hardware resources compared to that of conventional architectures.
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