The week's pick
Reseach Article
Simulation and Synthesis of Combinational Shifter using Reversible Gates
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 42 - Number 21 |
| Year of Publication: 2012 |
| Authors: Ravish Aradhya H V, Rekha G, Muralidhara K N |
10.5120/5832-7638
|
Ravish Aradhya H V, Rekha G, Muralidhara K N . Simulation and Synthesis of Combinational Shifter using Reversible Gates. International Journal of Computer Applications. 42, 21 ( March 2012), 1-7. DOI=10.5120/5832-7638
Abstract
In today's world, the complexity of the chip is increasing as more and more devices are being connected on a single chip. As the number of devices on the chip increases, the devices must be scaled so that they can be accommodated on a chip of small size. Due to the high density of the chip, the power dissipation increases demanding better power optimization methods. One of the methods to achieve power optimization is by using Reversible logic. It can be used in Low Power CMOS designs, Quantum Computing, Nanotechnology and Optical Computing. The objective of this work is to design a Combinational Logic Shifterthat is most often found in digital systems, where they are used to move data bits to new locations on a data bus or to perform simple multiplication and division operations. The performance characteristics of the two proposed designsare verified using number of reversible gates, Garbage outputs and Quantum Cost. The performanceCharacteristics analysis is carried out in cadence digital design environment and CMOS implementation in cadence virtuoso.
References
- . R. Landauer, "Irreversibilityand Heat Generation in the Computing Process", IBM Journal of Research and Development, vol. 3, pp. 183-191, July 1961.
- . C. H. Bennett, "Logical Reversibility of Computation", IBM Journal of Research andDevelopment, pp. 525-532, November 1973.
- . E. Fredkin, T Toffoli, "Conservative Logic", International Journal of Theoritical Physics, Vol. 21, 1982, pp. 219-253.
- . Yong Moon et al, "An Efficient Charge Recovery Logic Circuit", IEEE Journal of Solid-State Circuits, vol. 31, no. 4, April 1996.
- . D. P. Vasudevan, et al, "CMOS Realization of Online Testable Reversible Logic Gates", Proceedings of the IEEE Computer Society Annual Symposium on VLSI New Frontiers in VLSI Design,0-7695-2365-X/05, 2005.
- . HimanshuThapliyal, et al, "Transistor Realization of Reversible TSG Gate and Reversible Adder Architectures", Proceedings of the IEEE Computer Society Annual Symposium on VLSI New Frontiers in VLSI Design, 1-4244-0387-1/06, 2006.
- . William C. Athas and et al, "Low power digital systems based on adiabatic switching principles",IEEE transactions on VLSI systems, V-2, Issue-4, Dec-1994.
- . Sk. NoorMahammad and KamakotiVeezhinathan, "Constructing Online Testable Circuits Using Reversible Logic",IEEE Transactions on Instrumentation and Measurement, vol. 59, No. 1, January2010.
- . Mathew R. Pillmeier, Michael J. Schulte and E. GeorgeWaltersIII, "Design alternatives for barrel shifters", Computer Architecture and Arithmetic Laboratory, Computer Science and Engineering Department, Lehigh University, Bethlehem, PA 18015,USA.
- . Irina Hashmi and Hafiz Md. HasanBabu, "An Efficient Design of a Reversible Barrel Shifter",23rd International Conference on VLSI Design, 2010, pp. 93-98.
- . Sabyasachi Das and Sunil P. Khatri, "A Timing-Driven Approach to Synthesize Fast Barrel Shifters", IEEE Transactions on circuits and systems—ii: express briefs, vol. 55, no. 1, January 2008, pp. 31-35.
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